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Part: CXP402
Category:
Description: CMOS 4-bit Single Chip Microcomputer
Company: Sony Electronics
Datasheet: Download CXP402 datasheet File size : 186 kB
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CXP402
CMOS 4-bit Single Chip Microcomputer For the availability of this product, please contact the sales office.
Description The CXP402 is a CMOS 4-bit single chip microcomputer which consists of 4-bit CPU, ROM, RAM, 8-bit timer, 8-bit timer/counter, 18-bit time-base timer, LCD controller/driver, digital signal processor circuit for CD player, 1-bit DAC and the like. Features · Instruction cycle 1.89µs for 16.93MHz oscillation · ROM capacity 6144 × 8 bits · RAM capacity 400 × 4 bits (Including stack and display area) · LCD controller/driver (Enables to direct drive) · 8-bit timer, 8-bit timer/event counter and 18-bit time-base timer are incorporated; they are independently controllable. · Arithmetic and logical operations between the entire RAM area, I/O area and the accumulator by means of the memory mapped I/O. · Entire ROM area can be referred by the table lookup instruction. Digital Signal Processor (DSP) Block · Playback mode supporting CAV (Constant Angular Velocity) · Frame jitter free · Allows relative rotational velocity readout · Supports spindle external control · Wide capture range playback mode · Spindle rotational velocity following method · 16K RAM · EFM data demodulation · Enhanced EFM frame sync signal protection · SEC strategy-based error correction · Subcode demodulation and Sub Q data error detection · Digital spindle servo · 16-bit traverse counter · Asymmetry correction circuit · Servo auto sequencer · Digital audio interface output · Digital peak meter 112 pin LQFP (Plastic)
Digital Filter, DAC and Analog Low-Pass Filter Blocks · DBB (digital bass boost) function · Digital de-emphasis · Digital attenuation · Zero detection function · 8Fs oversampling digital filter · S/N: 100dB or more (master clock: 384Fs, typ.) Logical value: 109dB · THD + N: 0.007% or less (master clock: 384Fs, typ.) · Rejection band attenuation: 60dB or more · 112-pin plastic LQFP · Piggyback package (CXP401Z) available Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
1
E98924-PS
Block Diagram
COM3
SEG0
VLC2
VLC3
SEG1
VLC1
SCOR
XRSTO
SBSO
C4M
PCO
SEG2
COM0
EMPH
CNIN
MDP
VCTL
SEG3
COM1
GFS
SEIN
MDS
V16M
COM2
CLKO
MON
VCKI
AVSS
CLTV
AVDD
BIAS RF
XLTO
LOCK
VPCO2
FILO
FOK
DATO
EXCK
VPCO1
85 86 87 88 89 90 91 92 95 94 93 53 51 30 31 40 3 4 1 5 2 54 55 11 8 10 9 49 13 12 14 15 16 17 18 19 20 21 22 24 23 25 26
LCD Controller/Driver Servo Auto Sequencer PORT I/F INT PY0 PY1 PY2 PY3 EFM Demodulator SCOR EMPHI CPU I/F Digital CLV Digital PLL Asymmetry Collector 52 WFCK 38 GTOP 39 XPCK 41 RFCK 42 C2PO 45 XROF 48 MNT0 D/A I/F 47 MNT1 46 MNT3 50 DOUT 28 TEST0 27 TEST1 EPROM Collector 56 DTEST 57 CTEST 72 VDD Test Circuit 1-bit DAC Digital Filter RST 71 VSS 44 VDD 43 VSS 7 6 OSC VDD VSS Analog Out SQCK SQSO
SEG4 84
SEG5 83
SEG6 82
SEG7 81
SEG8 80
SPC500 CPU Core
SEG9 79
SEG10 78
SEG11 77 16K RAM
SEG12 76
SEG13 75
PB1
PB2
PB3
PB0
PC0
PC1
PC2
PC3
RMC
XTAI
AIN2
AVSS
AVSS
XVSS
AIN1
AVSS
XRST
AVDD
XVDD
XTAO
AVDD
AVSS
BCKI
BCK
PCMD
AOUT2
LOUT2
LOUT1
AOUT1
PCMDI
LRCKI
LRCK
2
SIO I/F RMC PX0 PX3 70 29
SEG14 74
SEG15 73
ROM 6K Byte
RAM 400 × 4bit
PA0 66
PF0 PF1 PF2 PF3 PE0 PE1 PE2 PE3 PD0 PD1 PD2
ACDT RMUT LMUT DATA XLAT CLOK XRST SYSM PWMI XTSL ASYE SENS FOK GFS
PA1 67
PA2 68
PA3 69
T/C
Port
62 63 64 65 58 59 60 61
111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 37 36 35 34 33 32
FILI
ASYI
ASYO
CXP402
CXP402
Pin Configuration (Top View)
AOUT2
LOUT2
LOUT1
AOUT1
COM0
COM1
COM2
COM3
XTAO
SEG0
SEG1
SEG2
AVDD
XTAI
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
SEG3
AVDD
XVDD
AVSS
AVSS
XVSS
AVSS
AIN2
AVSS
AIN1
VLC1
NC
VLC2
VLC3
SEIN CNIN DATO XLTO CLKO VSS VDD MON MDP MDS LOCK VPCO2 VPCO1 VCKI V16M VCTL PCO FILI FILO AVSS CLTV AVDD RF BIAS ASYI ASYO TEST1 TEST0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 VDD VSS RMC PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 CTEST
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
XRSTO
PCMDI
PCMD
WFCK
EMPH
SCOR
XROF
XPCK
SBSO
C2PO
RFCK
MNT3
MNT1
MNT0
XRST
EXCK
BCKI
GFS
C4M
FOK
BCK
VSS
3
DTEST
LRCKI
GTOP
DOUT
LRCK
VDD
CXP402
Pin Description Symbol PA0 to PA3 I/O I/O Description (Port A) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) (Port B) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) (Port C) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) LCD segment signal output. (16 pins) LCD common signal output. LCD bias power supply. Bias voltage is generated, which is 1/3 the supply voltage due to the internal resistor. (3 pins) Input Input Output Output Output Output Output (tri-state) Output Output (tri-state) Input Output Input SENS input from SSP. Track jump count signal input. Serial data output to SSP. Serial data latch output to SSP. Serial clock output to SSP. Spindle motor ON/OFF control output. Spindle motor servo control. (2 pins) Lock signal output. GFS is sampled at 460Hz and; when GFS is high, this pin outputs a high signal. If GFS is low eight convective samples, this pin outputs low. Wide-band EFM PLL charge pump output. (2 pins) Wide-band EFM PLL VCO2 oscillation input. Wide-band EFM PLL VCO2 oscillation output. Wide-band EFM PLL VCO2 control voltage input.
PB0 to PB3
I/O
PC0 to PC3 SEG0 to SEG15 COM0 to COM3 VLC1 to VLC3 SEIN CNIN DATO XLTO CLKO MON MDP MDS LOCK VPCO1 VPCO2 VCKI V16M VCTL PCO FILI FILO CLTV RF BIAS ASYI ASYO XRST
I/O Output Output
Output (tri-state) Master PLL charge pump output. Input Master PLL filter input.
Output (Analog) Master PLL filter output. Input Input Input Input Output Input Master VCO control voltage input. EFM signal input. Asymmetry circuit constant current input. Asymmetry comparator voltage input. EFM output. (full swing) System reset input. Active at low. 4
CXP402
Symbol XRSTO FOK LRCK LRCKI PCMD PCMDI BCK BCKI GTOP XPCK GFS RFCK C2PO XROF MNT3 MNT1 MNT0 C4M DOUT EMPH WFCK SCOR SBSO EXCK AOUT1 AIN1 LOUT1 AOUT2 AIN2 LOUT2 RMC XTAI XTAO NC
I/O Output Input Output Input Output Input Output Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input
Description Reset signal output. Active at low. Focus OK input. Used for SENS output and servo auto sequencer. D/A interface LR clock output. (f = Fs) LR clock input. D/A interface serial data output. D/A interface serial data input. D/A interface bit clock output. D/A interface bit clock input. GTOP output. XPLCK output. GFS output. RFCK output. C2PO output. XRAOF output. MNT3 output. MNT1 output. MNT0 output. 1/4 frequency division output of the oscillation input. (4.2336MHz for 16.3944MHz) Digital Out output. De-emphasis ON/OFF output. High is output for ON; low is output for OFF. WFCK output. Subcode sync detection output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial data output. SBSO serial clock input.
Output (Analog) Lch analog output. Input (Analog) Output Lch operational amplifier input. Lch LINE output.
Output (Analog) Rch analog output. Input (Analog) Output Input Input Rch operational amplifier Rch LINE output. Remote control receiver circuit input. Connect a crystal for system clock oscillation. When the clock is supplied externally, input it to the XTAI pin and leave the XTAO pin open. No connected. 5
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