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Part: ICX086AL
Category:
Description: Diagonal 4.5mm(Type 1/4)CCD Image Sensor For Eiab/w Video Cameras
Company: Sony Electronics
Datasheet: Download ICX086AL datasheet File size : 421 kB
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ICX086AL
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for EIA B/W Video Cameras
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Description The ICX086AL is an interline CCD solid-state image sensor suitable for EIA B/W video cameras. High sensitivity is achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip features a field period readout system and an electronic shutter with variable charge-storage time. The package is a 10mm-square 14-pin DIP (Plastic). Features · High sensitivity and low dark current · Horizontal register: 3.3 to 5.0V drive · No voltage adjustment (Reset gate and substrate bias are not adjusted.) · Low smear · Continuous variable-speed shutter Device Structure · Interline CCD image sensor · Image size: · Number of effective pixels: · Total number of pixels: · Chip size: · Unit cell size: · Optical black: · Number of dummy bits: · Substrate material: 14 pin DIP (Plastic)
in 1 1
V
2 Pin 8 H
P
12 25
Diagonal 4.5mm (Type 1/4) 510 (H) × 492 (V) approx. 250K pixels 537 (H) × 505 (V) approx. 270K pixels 4.47mm (H) × 3.80mm (V) 7.15µm (H) × 5.55µm (V) Horizontal (H) direction: Front 2 pixels, rear 25 pixels Vertical (V) direction: Front 12 pixels, rear 1 pixel Horizontal 16 Vertical 1 (even fields only) Silicon
Optical black position (Top View)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E96649D99
ICX086AL
VOUT
GND
V1
V2
V 3
7
6
5
4
3
2
Vertical Register
Horizontal Register Note) 8 9 10 11 12 13 14 : Photo sensor
GND
VDD
Pin Description Pin No. 1 2 3 4 5 6 7 Symbol V4 V3 V2 V1 NC GND VOUT GND Signal output Description
SUB
Pin No. 8 9 10 11 12 13 14
H1
H2
RG
VL
V 4
1 Note)
NC
Block Diagram and Pin Configuration (Top View)
Symbol VDD GND SUB VL RG H1 H2
Description Supply voltage GND Substrate clock Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock
Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock
Absolute Maximum Ratings Item Substrate clock SUB GND VDD, VOUT GND Supply voltage VDD, VOUT SUB V1, V2, V3, V4 GND Clock input voltage V1, V2, V3, V4 SUB Ratings 0.3 to +40 0.3 to +18 30 to +9 15 to +16 to +10 to +15 to +16 16 to +16 10 to +15 55 to +10 65 to +0.3 0.3 to +27.5 0.3 to +20.5 0.3 to +17.5 30 to +80 10 to +60 Unit V V V V V V V V V V V V V V °C °C 1 Remarks
Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H1, H2 V4 H1, H2 GND H1, H2 SUB VL SUB V1, V3, VDD, VOUT VL RG GND V2, V4, H1, H2, GND VL Storage temperature Operating temperature 1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. 2
ICX086AL
Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Symbol VDD VL SUB Min. 14.55 Typ. 15.0 1 2 Max. 15.45 Unit V Remarks
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol IDD Min. Typ. 4 Max. 6 Unit mA Remarks
Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage VVH3 VVH VVH4 VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage VH VHL VRG Reset gate clock voltage VRGLH VRGLL VRGH Substrate clock voltage VSUB 3.0 0.05 4.5 5.0 0 5.0 Min. 14.55 0.05 0.2 8.0 6.8 0.25 0.25 Typ. 15.0 0 0 7.5 7.5 Max. 15.45 0.05 0.05 7.0 8.05 0.1 0.1 0.3 0.3 0.3 0.3 5.25 0.05 5.5 0.8 VDD + VDD + VDD + 0.3 0.6 0.9 21.5 22.5 23.5 Unit V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Input through 0.01µF capacitance Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks
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