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Part: ICX096AKE
Category:
Description: Diagonal 3mm(Type 1/6) CCD Image Sensor For Ntsccolor Cameras
Company: Sony Electronics
Datasheet: Download ICX096AKE datasheet File size : 421 kB
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ICX096AKE
Diagonal 3mm (Type 1/6) CCD Image Sensor for NTSC Color Cameras
For the availability of this product, please contact the sales office.
Description The ICX096AKE is an interline CCD solid-state image sensor suitable for NTSC small color cameras. Ye, Cy, Mg, and G complementary color mosaic filters are used. At the same time, high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip features a field period readout system and an electronic shutter with variable chargestorage time. The package is a small 12-pin SON(LCC). Features · High sensitivity and low dark current · Horizontal register: 3.3 to 5.0V drive · No voltage adjustment (Reset gate and substrate bias are not adjusted.) · Low smear · Excellent antiblooming characteristics · Continuous variable-speed shutter · Recommended range of exit pupil distance: 10mm to · Ye, Cy, Mg, and G complementary color mosaic filters on chip · 12-pin ceramic SON(LCC) package Device Structure · Interline CCD image sensor · Image size: · Number of effective pixels: · Total number of pixels: · Chip size: · Unit cell size: · Optical black: · Number of dummy bits: · Substrate material: 12 pin SON (Ceramic)
in 1 1
V
2 Pin 7 H
P
12
25
Optical black position (Top View)
Diagonal 3mm (Type 1/6) 510 (H) × 492 (V) approx. 250K pixels 537 (H) × 505 (V) approx. 270K pixels 3.30mm (H) × 2.95mm (V) 4.80µm (H) × 3.75µm (V) Horizontal (H) direction: Front 2 pixels, rear 25 pixels Vertical (V) direction: Front 12 pixels, rear 1 pixel Horizontal 16 Vertical 1 (even fields only) Silicon
Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly
developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
1
E97601B0Y
ICX096AKE
VOUT
GND
V1
6
5
4
V 2
V3
3
2
Cy
Ye Mg Ye Mg Ye G
Cy G Cy G Cy Mg
Ye Mg Ye Mg Ye G
Vertical register
G Cy G Cy Mg
Horizontal register Note) 7 8 9 10 11 12 : Photo sensor
VD D
VL
RG
H1
Pin Description Pin No. 1 2 3 4 5 6 Symbol V4 V3 V2 V1 GND VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Signal output Pin No. 7 8 9 10 11 12 Symbol VD D SUB VL RG H1 H2 Description Supply voltage Substrate clock Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock
Absolute Maximum Ratings Item VDD SUB VOUT, RG SUB Against SUB V1, V3 SUB V2, V4, VL SUB H1, H2, GND SUB VDD, VOUT, RG GND Against GND V1, V2, V3, V4 GND H1, H2 GND Against VL V1, V3 VL V2, V4, H1, H2, GND VL Voltage difference between vertical clock input pins Between input clock pins Storage temperature Operating temperature 1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. H1 H2 H1, H2 V4 Ratings 40 to +8 40 to +10 50 to +15 50 to +0.3 40 to +0.3 0.3 to +18 10 to +18 10 to +15 0.3 to +26 0.3 to +16 to +15 14 to +14 14 to +14 30 to +80 10 to +60 Unit V V V V V V V V V V V V V °C °C 1 Remarks
SUB
2
H 2
V 4
1 Note)
Block Diagram and Pin Configuration (Top View)
ICX096AKE
Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Symbol VDD VL SUB Min. 14.55 Typ. 15.0 1 2 Max. 15.45 Unit V Remarks
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol I DD Min. Typ. 4 Max. 6 Unit mA Remarks
Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage VVH3 VVH VVH4 VVH VV H H VVHL VVLH VVLL Horizontal transfer clock voltage VH VHL VRG Reset gate clock voltage VRGLH VRGLL VRGH Substrate clock voltage VSUB 3.0 0.05 4.5 5.0 0 5.0 Min. 14.55 0.05 0.2 8.0 6.8 0.25 0.25 Typ. 15.0 0 0 7.5 7.5 Max. 15.45 0.05 0.05 7.0 8.05 0.1 0.1 0.3 0.3 0.3 0.3 5.25 0.05 5.5 0.8 VDD + VDD + VDD + 0.3 0.6 0.9 21.5 22.5 23.5 Unit V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Input through 0.01µF capacitance Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks
3
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