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Part: ICX098AK
Category:
Description: Diagonal 4.5mm(Type 1/4)Progressive Scan CCD Imagesensor With Square Pixel For Color Cameras
Company: Sony Electronics
Datasheet: Download ICX098AK datasheet File size : 421 kB
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ICX098AK
Diagonal 4.5mm (Type 1/4) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
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Description The ICX098AK is a diagonal 4.5mm (Type 1/4) interline CCD solid-state image sensor with a square pixel array which supports VGA format. Progressive scan allows all pixels signals to be output independently within approximately 1/30 second. Also, the adoption of monitoring mode allows output to an NTSC monitor without passing through the memory. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still image without a mechanical shutter. High resolution and high color reproductivity are achieved through the use of R, G, B primary color mosaic filters. Further, high sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip is suitable for applications such as electronic still cameras, PC input cameras, etc. Features · Progressive scan allows individual readout of the image signals from all pixels. · High horizontal and vertical resolution (both approx. 400TV-lines) still image without a mechanical shutter. · Supports monitoring mode · Square pixel · Supports VGA format · Horizontal drive frequency: 12.27MHz · No voltage adjustments (reset gate and substrate bias are not adjusted.) · R, G, B primary color mosaic filters on chip · High resolution, high color reproductivity, high sensitivity, low dark current · Continuous variable-speed shutter · Low smear · Excellent antiblooming characteristics · Horizontal register: 3.3V drive · 14-pin high precision plastic package (enables dual-surface standard) Device Structure · Interline CCD image sensor · Image size: · Number of effective pixels: · Total number of pixels: · Chip size: · Unit cell size: · Optical black: · Number of dummy bits: · Substrate material: 14 pin DIP (Plastic)
in 1 2
V
2 Pin 8
H
P
8 31
Optical black position (Top View)
Diagonal 4.5mm (Type 1/4) 659 (H) × 494 (V) approx. 330K pixels 692 (H) × 504 (V) approx. 350K pixels 4.60mm (H) × 3.97mm (V) 5.6µm (H) × 5.6µm (V) Horizontal (H) direction: Front 2 pixels, rear 31 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels Horizontal 16 Vertical 5 Silicon
Wfine CCD is a registered trademark of Sony Corporation. Represents a CCD adopting progressive scan, primary color filter and square pixel. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
1
E96533C0Y-PS
ICX098AK
VOUT
GND
V 2 B
V2A
7
6
VL
5
V 3
4
3
2
G
B G B G B G
G R G R G R
B G B G B G
Vertical register
R G R G R
Horizontal register Note) : Photo sensor
8
9
10
11
12
13
Pin Description Pin No. 1 2 3 4 5 6 Symbol V1 V3 V2A V2B VL GND
Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Protective transistor bias GND
S U B
CSUB
GND
Pin No. 8 9 10 11 12 13
R G
VDD
Symbol VDD GND SUB CSUB RG H1
H1
H 2
V 1
1 Note) 14
Block Diagram and Pin Configuration (Top View)
Description Supply voltage GND Substrate clock Substrate bias1 Reset gate clock Horizontal register transfer clock
7 VOUT H2 Horizontal register transfer clock Signal output 14 1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF. Absolute Maximum Ratings Item VDD, VOUT, RG SUB V2A, V2B SUB Against SUB V1, V3, VL SUB H1, H2, GND SUB CSUB SUB VDD, VOUT, RG, CSUB GND Against GND V1, V2A, V2B, V3 GND H1, H2 GND Against VL V2A, V2B VL V1, V3, H1, H2, GND VL Voltage difference between vertical clock input pins Between input H1 H2 clock pins H1, H2 V3 Storage temperature Operating temperature 2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. 2 Ratings 40 to +10 50 to +15 50 to +0.3 40 to +0.3 25 to 0.3 to +18 10 to +18 10 to +5 0.3 to +28 0.3 to +15 to +15 5 to +5 13 to +13 30 to +80 10 to +60 Unit V V V V V V V V V V V V V °C °C 2 Remarks
ICX098AK
Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock Symbol VDD VL SUB RG Min. 14.55 Typ. 15.0 1 2 2 Max. 15.45 Unit V Remarks
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.
DC Characteristics Item Supply current Symbol IDD Min. Typ. 6.0 Max. Unit mA Remarks
Clock Voltage Conditions Item Readout clock voltage VVT VVH02A VVH1, VVH2A, VVH2B, VVH3 VVL1, VVL2A, VVL2B, VVL3 Vertical transfer clock voltage V1, V2A, V2B, V3 | VVL1 VVL3 | VV H H VVHL VVLH VVLL Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage VH VHL VRG VRGLH VRGLL VRGL VRGLm VSUB 19.75 20.5 3.0 0.05 3.0 3.3 0 3.3 Symbol Min. 14.55 0.05 0.2 5.8 5.2 Typ. 15.0 0 0 5.5 5.5 Max. 15.45 0.05 0.05 5.2 5.8 0.1 0.3 1.0 0.5 0.5 5.25 0.05 5.5 0.4 0.5 21.25 Unit V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Low-level coupling Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL1+VVL3)/2 VVH = VVH02A Remarks
3
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