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Part: ICX413AQ
Category:
Sensors
-> Image Sensors
-> CCD
Description: Diagonal 28.40mm(Type 1.8) Frame Readout Ccdimage Sensor With Square Pixel For Color Cameras
Company: Sony Electronics
Datasheet: Download ICX413AQ datasheet File size : 421 kB
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ICX413AQ
Diagonal 28.40mm (Type 1.8) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
Description The ICX413AQ is a diagonal 28.40mm (Type 1.8) interline CCD solid-state image sensor with a square pixel array and 6.15M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/3.08 second. Adoption of a design specially suited for frame readout ensures a high saturation signal level. High sensitivity and low dark current are achieved through the adoption of R, G and B primary color mosaic filters and HAD (Hole-Accumulation Diode) sensors. T h i s chip is suitable for applications such as electronic still cameras, etc. Features · Frame readout mode · High horizontal and vertical resolution · Square pixel · Horizontal drive frequency: 25.0MHz · R, G, B primary color mosaic filters on chip · High sensitivity, low dark current 34 pin DIP (Plastic)
Pin 1 2 V
4 20 H Pin 18 50
Optical black position Device Structure (Top View) · Interline CCD image sensor · Optical size: Diagonal 28.40mm (Type 1.8) · Total number of pixels: 3110 (H) × 2030 (V) approx. 6.31M pixels · Number of effective pixels: 3040 (H) × 2024 (V) approx. 6.15M pixels · Number of active pixels: 3032 (H) × 2016 (V) approx. 6.11M pixels · Number of recommended recording pixels: 3000 (H) × 2000 (V) approx. 6M pixels · Chip size: 25.10mm (H) × 17.64mm (V) · Unit cell size: 7.80µm (H) × 7.80µm (V) · Optical black: Horizontal (H) direction: Front 20 pixels, rear 50 pixels Ver tical (V) direction: Front 4 pixels, rear 2 pixels · Number of dummy bits: Horizontal 31 Ver tical 1 (even fields only) · Substrate material: Silicon
Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
1
E02120B35
ICX413AQ
Block Diagram and Pin Configuration (Top View)
GND GND GND VSUB V 1 V 2 V 3 V 4 NC NC NC NC NC NC NC NC
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
G
Ver tical register
B G B G B G
G R G R G R
B G B G B G Note)
R G R G R
Horizontal register
VL
1
Note) 18
VSS
: Photo sensor
19
VOUT
20
GND
21
RG
22
GND
23
VDD
24
GND
25
LH
26
H1C
27
H2C
28
GND
29
H1B
30
H2B
31
GND
32
H1A
33
H2A
34
GND
Pin Description Pin Symbol No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VL GND NC NC V4 NC V3 NC GND V2 NC NC NC V1 NC GND V SUB GND Substrate bias Ver tical register transfer clock GND Ver tical register transfer clock Ver tical register transfer clock Ver tical register transfer clock GND Descr iption Protective transistor bias Pin Symbol No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VSS VOUT GND RG GND VDD GND LH H1C H2C GND H1B H2B GND H1A H2A GND 2 Signal output GND Reset gate clock GND Supply voltage GND Horizontal register final stage transfer clock Horizontal register transfer clock Horizontal register transfer clock GND Horizontal register transfer clock Horizontal register transfer clock GND Horizontal register transfer clock Horizontal register transfer clock GND Descr iption Output amplifier source
ICX413AQ
Absolute Maximum Ratings Item VDD, VOUT, RG SUB Against SUB V1, V3 SUB V2, V4, VL SUB LH, H1, H2, GND SUB ( = VDD, VOUT, RG GND Against GND V1, V2, V3, V4 GND LH, H1, H2 GND ( = Against VL V1, V3 VL V2, V4, LH, H1, H2, GND VL ( = H1 H2 ( =
A, B, C) A, B, C) A, B, C)
Ratings 40 to +10 50 to +15 50 to +0.3 40 to +0.3 0.3 to +18 10 to +18 10 to +7 0.3 to +28 0.3 to +15 to +15 7 to +7 17 to +17 30 to +80 10 to +60 10 to +75
Unit V V V V V V V V V V V V °C °C °C
Remar ks
Voltage difference between vertical clock input pins Between input clock pins
A, B, C) A, B, C)
1
H1, H2 V4 ( =
Storage temperature Guaranteed temperature of performance Operating temperature 1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
Bias Conditions Item Supply voltage Output amplifier source Protective transistor bias Reset gate clock Symbol VDD V SS VL RG Min. 14.55 8.0 1 2 Typ. 15.0 Max. 15.45 15.0 Unit V Remar ks
Ground with resistance of 750 to 900
Substrate voltage adjustment range VSUB
1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the reset gate clock pins, because a DC bias is generated within the CCD.
DC Characteristics Item Supply current Symbol IDD Min. Typ. 7.0 Max. Unit mA Remar ks
3
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