Description The is a diagonal 28.40mm (Type 1.8) interline CCD solid-state image sensor with a square pixel array and 6.15M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/3.08 second. Adoption of a design specially suited for frame readout ensures a high saturation signal level. High sensitivity and low dark current are achieved through the adoption R, G and B primary color mosaic filters and HAD (Hole-Accumulation Diode) sensors. This chip is suitable for applications such as electronic still cameras, etc. Features· Frame readout mode· High horizontal and vertical resolution· Square pixel· Horizontal drive frequency: G, B primary color mosaic filters on chip· High sensitivity, low dark current 34 pin DIP (Plastic)

Optical black position Device Structure (Top View)· Interline CCD image sensor· Optical size: Diagonal 28.40mm (Type 1.8)· Total number of pixels: 3110 (H) × 2030 (V) approx. 6.31M pixels· Number of effective pixels: 3040 (H) × 2024 (V) approx. 6.15M pixels· Number of active pixels: 3032 (H) × 2016 (V) approx. 6.11M pixels· Number of recommended recording pixels: 3000 (H) × 2000 (V) approx. 6M pixels· Chip size: 25.10mm (H) × 17.64mm (V)· Unit cell size: 7.80µm (H) × 7.80µm (V)· Optical black: Horizontal (H) direction: Front 20 pixels, rear 50 pixels Vertical (V) direction: Front 4 pixels, rear 2 pixels· Number of dummy bits: Horizontal 31 Vertical 1 (even fields only)· Substrate material: Silicon

Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Pin Description Pin Symbol No. VL GND V3 NC GND V1 NC GND VSUB GND Substrate bias Vertical register transfer clock GND Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Description Protective transistor bias Pin Symbol No. VSS VOUT GND RG GND VDD GND H1C H2C GND H1B H2B GND H1A H2A GND ­2­ Signal output GND Reset gate clock GND Supply voltage GND Horizontal register final stage transfer clock Horizontal register transfer clock Horizontal register transfer clock GND Horizontal register transfer clock Horizontal register transfer clock GND Horizontal register transfer clock Horizontal register transfer clock GND Description Output amplifier source

Absolute Maximum Ratings Item VDD, VOUT, RG ­ SUB Against SUB V3 ­ SUB VL ­ SUB LH, H1, H2, GND ­ SUB ( = VDD, VOUT, RG ­ GND Against GND V4 ­ GND LH, H2 ­ GND ( = Against V2, V4, LH, H1, H2, GND ­ VL

Storage temperature Guaranteed temperature of performance Operating temperature 1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Bias Conditions Item Supply voltage Output amplifier source Protective transistor bias Reset gate clock Symbol VDD VSS VL RG Min. Typ. 15.0 Max. 15.45 15.0 Unit V Remarks

1 VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the reset gate clock pins, because a DC bias is generated within the CCD.