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Details, datasheet, quote on part number:SA9401
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| Part: | SA9401 |
| Category: | Communication => Telephony => Tone Generator |
| Description: | Universal Pabx Tone Generator |
| Company: | South African Micro-Electronic Systems |
| Datasheet: | Download SA9401 datasheet File size : 126 kB |
| Request For quote: | Find where to buy SA9401
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Datasheet text preview:
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FEATURES s Generates PBX supervisory tones in PCM format
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SA9401
UNIVERSAL PABX TONE GENERATOR
Each of these tone streams selectable from 16 tone blocks Seperate Intrude Tone for each program Choice of clock frequencies Watchdog facility Low power CMOS technology
Integrated time slot allocation circuitry No noticeable level changes in tones Frame synch. signal source (internal/ external) selectable Eight tone programs Eight independent PCM tone streams within each program
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PROGRAMMABLE FEATURES s Tone samples
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Intrude tone frequency Intrude tone cadence "silence sample" value
Tone Cadence timing Tone to time-slot mapping Size of tone blocks
DESCRIPTION The SA9401 operates in conjunction with a standard EPROM to generate the system tone plans for the PABX systems of most major countries. The high level of programmability allows the SA9401 to satisfy a wide variety of tone plans. Furthermore by providing three inputs to select between one of eight tone programs during initialisation, the device effectively facilitates the design of a universally programmable "PABX Processor Card". Because the tone program inputs are latched at the start of each PCM frame the SA9401 minimises the possibility of glitches. The SA9401 can also generate the PCM Frame synchronising reference signal if required.
4092
PDS039-SA9401-001
REV. C
07-05-96
SA9401
A7 MRST D0 D1 D2 V CC D3 D4 D5 D6 D7
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
CLK_SEL A0 A1 A2 A3 GND A4 A5 A6 PCMFSC CLKIN
40 41 42 43 44 1 2 3 4 5 6
SA9401
23 22 21 20 19 18
TEST FS1 A8 A9 A11 GND A10 A12 A13 PS2 WD_INT
7
8
9
10
11 12 13 14 15
16 17
DR-00603
Package : PLCC - 44
PIN DESCRIPTION
Pin No
1, 23 12, 34 27 6 8 10 5 11 13 15 41, 42, 43, 44, 2, 3, 4, 39, 26, 25, 22, 24, 21, 20
I/0
I I I I O O O O O O O
Designation
GND VCC FS1 CLKIN 2MCLK 8KFS PCMFSC INTRFRQ INTRCAD PCM_OUT A0..A13
2
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CLKDIV2 2MCLK PS0 8KFS INTRFRQ VCC INTRCAD PS1 PCM_OUT WD_RST WD_EN
Description
Supply Ground +5V Power Supply Frame Synchronisation (active low) Master clock input (either 8192kHz or 2048 Khz dependent on logic level of "CLK _SEL") 2048 kHz clock derived internally from CLKIN 8 kHz Frame Synchronisation output. 8 kHz Auxilliary Frame Synchronisation Output Square Wave Intrude Tone Intrude Tone Cadence Signal Tri-state PCM Highway tone output EPROM Address Lines
SA9401
PIN DESCRIPTION (Continued)
Pin No
37, 36, 35, 33, 32, 31, 30, 29 9, 14, 19 7 40
I/0
I I O I
Designation
D0..D7 PS0, PS1, PS2 CLKDIV2 CLK_SEL
Description
EPROM Data Lines Program Select Inputs for Selecting between 1 of 8 tone plans CLKIN divided by 2 output (i.e. 4096 kHz or 1024 kHz depending on CLK_SEL input) Selects between CKLIN of 8192 or 2048 kHz and Synchronisation source. 0 = 8192kHz/Internal 1 = 2048kHz/External Used for IC testing purpose. Tied Low during normal operation. Asynchronous Reset Pin. Resets all Internal Flip Flops (active low) Watchdog reset input (Rising-edge triggered) Tied high if unused Watchdog enable input (active low) Tied high if unused Watchdog output (active low, tri-state)
28 38 16 17 18
I I I I O
TEST MRST WD_RST WD_EN WD_INT
BLOCK DIAGRAM
CLKDIV2 /MRST CLK_SEL CLKIN
CLOCK GENERATOR
2MCLK 8KFS PCMFSC
WD_RST WDENB D[7 : 0]
WATCHDOG TIMER
WD_INT
INTRUDE TONE GENERATOR
INTRFRQ
/FS1
CADENCE TIMER
INTRCAD
PS[2 : 0]
EPROM INTERFACE
A [ 1 3 : 0]
TEST
PCM INTERFACE SA9401
DR-01085
PCM_OU
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