Details, datasheet, quote on part number: 68901Q05
Part68901Q05
Category
DescriptionMulti.function Peripheral
CompanyST Microelectronics, Inc.
DatasheetDownload 68901Q05 datasheet
  

 

Features, Applications

8 INPUT/OUTPUT PINS Individually programmable direction Individual interrupt source capability - Programmable edge selection 16 SOURCE INTERRUPT CONTROLLER 8 Internal sources 8 External sources Individual source enable Individual source masking Programmable interrupt service modes - Polling - Vector generation - Optional In-service status Daisy chaining capability FOUR TIMERS WITH INDIVIDUALLY PROGRAMMABLE PRESCALING Two multimode timers - Delay mode - Pulse width measurement mode - Event counter mode Two delay mode timers Independent clock input Time out output option SINGLE CHANNEL USART Full Duplex Asynchronous to 65 kbps Byte synchronous to 1 Mbps Internal/External baud rate generation DMA handshake signals Modem control Loop back mode 68000 BUS COMPATIBLE 48 PIN DIP OR 52 PIN PLCC

DESCRIPTION The MK68901 MFP (Multi-Function Peripheral) is a combination of many of the necessary peripheral functions in a microprocessor system. Included are : Eight parallel I/O lines Interrrupt controller for 16 sources Four timers Single channel full duplex USART The use of the MFP in a system can significantly reduce chip count, thereby reducing system cost. The MFP is completely 68000 bus compatible, and 24 directly addressable internal registers provide the neDecember 1988

necessary control and status interface to the programmer. The MFP is a derivative of the MK3801 STI, a Z80 family peripheral. PIN DESCRIPTION GND : Ground VCC : +5 volts 5%) Chip Select (input, active, low). CS is used to select the MK68901 MFP for accesses to the internal registers. CS and IACK must not be asserted at the same time. DS : Data Strobe (input, active low). DS is used as part of the chip select and interrupt acknowledge functions. R/W : Read/Write (input). R/W is the signal from the bus master indicating whether the current bus cycle is a Read (High) or Write (Low) cycle. DTACK : Data Transfer Acknowledge. (output, active low, tri-stateable) DTACK is used to signal the bus master that data is ready, or that data has been accepted by the MK68901 MFP. A1-A5 : Address Bus (inputs). The adress bus is used to adress one of the internal registers during a read or write cycle. Data Bus (bi-directional, tri-stateable). The data bus is used to receive data from or transmit data to one of the internal registers during a read or write cycle. It is also used to pass a vector during an interrupt acknowledge cycle. Clock (input). This input is used to provide the internal timing for the MK68901 MFP. IACK :

knowledge cycle or by clearing the pending interrupt(s) through software. Interrupt Acknowledge (input, active low). IACK is used to signal the MK68901 MFP that the CPU is acknowledging an interrupt. CS and IACk must not be asserted at the same time. Interrupt Enable In (input, active low). IEI is used to signal the MK68901 MFP that no higher priority device is requesting interrupt service. Interrupt Enable Out (output, active low). IEO is used to signal lower priority peripherals that neither the MK68901 MFP nor another higher priority peripheral is requesting interrupt service. General Purpose Interrupt I/O lines. These lines may be used as interrupt inputs and/or I/O lines. When used as interrupt inputs, their active edge is programmable. A data direction register is used to define which lines are to be Hi-Z inputs and which lines are to be push-pull TTL compatible outputs. Serial Output. This is the output of the USART transmitter. Serial Input. This is the input to the USART receiver. Receiver Clock. This input controls the serial bit rate of the USART receiver. Transmitter Clock. This input controls the serial bit rate of the USART transmitter. Receiver Ready. (output, active low) DMA output for receiver, which reflects the status of Buffer Full in port number 15. Transmitter Ready. (output, active low) DMA output for transmitter, which reflects the status of Buffer Empty in port number 16.

RESET : Device reset. (input, active low). Reset disables the USART receiver and transmitter, stops all timers and forces the timer outputs low, disables all interrupt channels and clears any pending interrupts. The General Purpose Interrupt/I/O lines will be placed in the tri-state input mode. All internal registers (except the timer, USART data registers, and transmit status register) will be cleared. INTR : Interrupt Request (output, active low, open drain). INTR is asserted when the MK68901 MFP is requesting an interrupt. INTR is negated during an interrupt ac2/33

TAO,TBO, Timer Outputs. Each of the four timers TCO,TDO: has an output which can produce a square wave. The output will change states each timer cycle ; thus one full period of the timer out signal is equal to two timer cycles. TAO or TBO can be reset (logic "O") by a write to TACR, or TBCR respectively. XTAL2 : Timer Clock inputs. A crystal can be connected between XTAL1 and or XTAL1 can be driven with a TTL level clock. When driving XTAL1 with a TTL le-

vel clock, XTAL2 must be allowed to float. When using a crystal, external capacitors are required. See figure 33. All chip accesses are independent of the timer clock. TAI,TBI : Timer A, B inputs. Used when running the timers in the event count or the pulse width measurement mode. The interrupt channels associated with 14 and 13 are used for TAI and TBI, respectively. Thus, when running a timer in the pulse width


 

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