|
Details, datasheet, quote on part number:74AC138TTR
| |
Datasheet text preview:
74AC138
3 TO 8 LINE DECODER (INVERTING)
s s
s
s
s
s
s
s
s
H IGH SPEED: tPD = 4.5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C H IGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74AC138B 74AC138M T&R 74AC138MTR 74AC138TTR
DESCRIPTION The 74AC138 is an advanced high-speed CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high. Tree enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/10
74AC138
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 2, 3 4, 5 6 15, 14, 13, 12, 11, 10, 9, 7 8 16 SYMBOL A, B, C G2A, G2B G1 Y0 to Y7 NAME AND FUNCTION Address Inputs Enable Inputs Enable Input Outputs
GND V CC
Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS OUTPUTS ENABLE G2B X X H L L L L L L L L G2A X H X L L L L L L L L G1 L X X H H H H H H H H C X X X L L L L H H H H SELECT B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L
X : Don't Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/10
74AC138
AB SOLUTE MAXIMUM RATINGS
Symbol V CC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA °C °C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1) Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 8 Unit V V V °C ns/V
1) VIN from 30% to 70% of V CC
3/10
74AC138
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 II ICC IOLD IOHD Input Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 VO = 0.1 V or VCC-0.1V VO = 0.1 V or VCC-0.1V IO=-50 µA IO=-50 µA IO=-50 µA IO=-12 mA IO=-24 mA IO=-24 mA IO=50 µA IO=50 µA IO=50 µA IO=12 mA IO=24 mA IO=24 mA VI = VCC or GND VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 2.9 4.4 5.4 2.56 3.86 4.86 0.002 0.001 0.001 0.1 0.1 0.1 0.36 0.36 0.36 ± 0.1 4 TA = 25°C Min. 2.1 3.15 3.85 Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 Max. Value -40 to 85°C Min. 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1 40 75 -75 0.9 1.35 1.65 2.9 4.4 5.4 2.4 3.7 4.7 0.1 0.1 0.1 0.5 0.5 0.5 ±1 80 50 -50 µA µA mA mA V V Max. -55 to 125°C Min. 2.1 3.15 3.85 0.9 1.35 1.65 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
V
VOH
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
4/10
74AC138
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 3.3
(*)
Value TA = 25°C Min. 1.5 1.5 1.5 1.5 1.5 1.5 Typ. 5.5 4.5 6.0 4.5 5.5 4.5 Max. 10.5 9.0 10.5 11.0 10.5 9.0 -40 to 85°C Min. 1.5 1.5 1.5 1.5 1.5 1.5 Max. 14.0 10.0 14.0 10.0 12.7 10.0 -55 to 125°C Min. 1.5 1.5 1.5 1.5 1.5 1.5 Max. 15.4 11.0 15.4 11.0 14.0 10.0 ns ns ns Unit
tPLH tPHL Propagation Delay Time A, B, C to Y tPLH tPHL Propagation Delay Time G1 to Y tPLH tPHL Propagation Delay Time G2A or G2B to Y
(*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V
5.0(**) 3.3(*) 5.0
(**)
3.3(*) 5.0(**)
CA PACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 5.0 fIN = 10MHz 60 pF TA = 25°C Min. Typ. 4 Max. Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit)
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
5/10
|
|