HIGH SPEED: tPD = 4.5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC TA=25°C 50 TRASMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 14 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION The is an advanced high-speed CMOS HEX SCHMITT TRIGGER INVERTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
This together with its schmitt trigger function allows to be used on line receivers with slow rise/fall input signals. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN No SYMBOL to 6Y GND VCC NAME AND FUNCTION Data Inputs Data Outputs Ground (0V) Positive Supply Voltage
Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to VCC -0.5 to VCC +150 300 Unit mA °C
ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
Symbol VCC VI VO Top Supply Voltage Input Voltage Output Voltage Operating Temperature Parameter Value 0 to VCC 0 to VCC to 125 Unit V °C
High Level Input Voltage Low Level Input Voltage Hysteresis Voltage
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50