HIGH SPEED: fMAX = 200MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL 28 % VCC (MIN.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 163 IMPROVED LATCH-UP IMMUNITY

DESCRIPTION The is an advanced high-speed CMOS SYNCRONOUS PRESETTABLE COUNTER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. a 4 bit binary counter with Synchronous Clear. The circuit have four fundamental modes of operation, in order of preference: synchronous reset, parallel load, count-up and hold. Four control inputs, Master Reset (CLEAR), Parallel Enable Input (LOAD), Count Enable Input (PE) and Count Enable Carry Input (TE), determine the PIN CONNECTION AND IEC LOGIC SYMBOLS

mode of operation as shown in the Truth Table. A LOW signal on CLEAR overrides counting and parallel loading and sets all outputs on LOW state on the next rising edge of CLOCK. A LOW signal on LOAD overrides counting and allows information on Parallel Data inputs to be loaded into the flip-flop on the next rising edge of CLOCK. With LOAD and CLEAR HIGH, PE and TE permit counting when both are HIGH. Conversely, a LOW signal on either PE and TE inhibits counting. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

PIN No SYMBOL CLEAR CLOCK PE TE LOAD to QD NAME AND FUNCTION Master Reset Clock Input (LOW to HIGH Edge Trigger) Data Inputs Count Enable Input Count Enable Carry Input Parallel Enable Input Flip-Flop Outputs