HIGH SPEED: tPD 4.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC 8 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16541 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION The is an advanced high-speed CMOS 16-BIT BUS BUFFER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. This is composed of two 8-bit sections with separate output-enable signals. For either 8-bit buffers section, the 3 STATE control gate operates as a two input AND such that if either nG1 and nG2 are high, all outputs are in the high impedence state.
1G1, 1G2 Output Enable Inputs to 1Y8 Data Outputs to 2Y8 Data Outputs 2G1, 2G2 Output Enable Inputs to 2A8 Data Outputs to 1A8 Data Outputs GND VCC Ground (0V) Positive Supply Voltage
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to VCC +150 300 Unit mA °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 1) VCC or 5.5 Parameter Value 0 to VCC 0 to VCC to 8 Unit V °C ns/V