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Part: 74AC574TTR
Category:
Logic
-> CMOS/BiCMOS->AC/ACT Family->Advanced High Speed CM
Description: Octal D-type Flip Flop With 3-STATE Output Non Inverting
Company: ST Microelectronics, Inc.
Datasheet: Download 74AC574TTR datasheet File size : 232 kB
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Datasheet text preview:
74AC574
OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS (NON INVERTED)
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H IGH SPEED: fMAX = 250MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C H IGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74AC574B 74AC574M T&R 74AC574MTR 74AC574TTR
DESCRIPTION The 74AC574 is an advanced high-speed CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type Flip-Flop are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic that were setup at the D inputs. PIN CONNECTION AND IEC LOGIC SYMBOLS
W hile the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
April 2001
1/11
74AC574
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 Q0 to Q7 NAME AND FUNCTION 3-State Output Enable (Active LOW) Data Inputs 3-State Outputs
CLOCK GND VC C
Clock Input (LOW-to-HIGH Edge Trigger) Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS OE H L L L
X : Don't Care Z : High Impedance
OUTPUT D X X L H Q Z NO CHANGE L H
CK X
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/11
74AC574
AB SOLUTE MAXIMUM RATINGS
Symbol V CC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA °C °C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1) Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 8 Unit V V V °C ns/V
1) VIN from 30% to 70% of V CC
3/11
74AC574
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 II Ioz Input Leakage Current High Impedance Output Leakege Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 5.5 VO = 0.1 V or VCC-0.1V VO = 0.1 V or VCC-0.1V IO=-50 µA IO=-50 µA IO=-50 µA IO=-12 mA IO=-24 mA IO=-24 mA IO=50 µA IO=50 µA IO=50 µA IO=12 mA IO=24 mA IO=24 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 2.9 4.4 5.4 2.56 3.86 4.86 0.002 0.001 0.001 0.1 0.1 0.1 0.36 0.36 0.36 ± 0.1 ± 0.5 4 TA = 25°C Min. 2.1 3.15 3.85 Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 Max. Value -40 to 85°C Min. 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1 ± 2.5 40 75 -75 0.9 1.35 1.65 2.9 4.4 5.4 2.4 3.7 4.7 0.1 0.1 0.1 0.5 0.5 0.5 ±1 ±5 80 50 -50 µA µA µA mA mA V V Max. -55 to 125°C Min. 2.1 3.15 3.85 0.9 1.35 1.65 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
V
VOH
ICC IOLD IOHD
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
4/11
74AC574
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 3.3
(*)
Value TA = 25°C Min. Typ. 6.5 5.0 7.0 5.0 6.5 5.0 1.5 1.5 -0.5 0 0.5 0 75 95 220 250 Max. 13.5 9.5 11.0 8.5 12.0 9.5 6.0 4.0 2.5 1.5 2.5 1.5 60 85 -40 to 85°C Min. Max. 15.0 11.0 12.0 9.0 13.0 10.5 7.0 5.0 3.0 2.0 3.0 2.0 60 85 -55 to 125°C Min. Max. 16.5 11.5 13.0 9.5 14.0 11.5 7.0 5.0 3.0 2.0 3.0 2.0 ns ns Unit
tPLH tPHL Propagation Delay Time CK to Q tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time tW CLOCK Pulse Width HIGH or LOW Setup Time D to CK, HIGH or LOW Hold Time D to CK, HIGH or LOW Maximum Clock Frequency
5.0(**) 3.3(*) 5.0
(**)
ns
3.3(*) 5.0
(**)
ns
3.3(*) 5.0
(**)
ts th fMAX
3.3(*) 5.0
(**)
ns ns
3.3(*) 5.0(**) 3.3(*) 5.0
(**)
MHz
(*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V
CA PACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 5.0 5.0 fIN = 10MHz TA = 25°C Min. Typ. 4 8 18 Max. Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. pF pF pF Unit
CIN CO U T CPD
Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit)
5/11
Others parts begin by 74
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