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Part: 74AC74
Category:
Logic
-> CMOS/BiCMOS->AC/ACT Family->Advanced High Speed CM
Description: Dual D-type Flip Flop With Preset And Clear
Company: ST Microelectronics, Inc.
Datasheet: Download 74AC74 datasheet File size : 232 kB
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Datasheet text preview:
74AC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
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H IGH SPEED: fMAX = 300MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C H IGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE 74AC74B 74AC74M T&R 74AC74MTR 74AC74TTR
DESCRIPTION The 74AC74 is an advanced high-speed CMOS DU AL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. A signal on the D INPUT is transferred to the Q and Q OUTPUTS during the positive going
transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
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74AC74
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage
4, 10 5, 9 6, 8 7 14
1PR, 2PR 1Q, 2Q 1Q, 2Q GND V CC
TRUTH TABLE
INPUTS CLR L H L H H H
X : Don't Care
OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn NO CHANGE CLEAR PRESET
PR H L L H H H
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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74AC74
AB SOLUTE MAXIMUM RATINGS
Symbol V CC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 200 -65 to +150 300 Unit V V V mA mA mA mA °C °C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1) Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 8 Unit V V V °C ns/V
1) VIN from 30% to 70% of V CC
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74AC74
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 II ICC IOLD IOHD Input Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 5.5 5.5 5.5 VO = 0.1 V or VCC-0.1V VO = 0.1 V or VCC-0.1V IO=-50 µA IO=-50 µA IO=-50 µA IO=-12 mA IO=-24 mA IO=-24 mA IO=50 µA IO=50 µA IO=50 µA IO=12 mA IO=24 mA IO=24 mA VI = VCC or GND VI = VCC or GND VOLD = 1.65 V max VOHD = 3.85 V min 2.9 4.4 5.4 2.56 3.86 4.86 0.002 0.001 0.001 0.1 0.1 0.1 0.36 0.36 0.36 ± 0.1 2 TA = 25°C Min. 2.1 3.15 3.85 Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 Max. Value -40 to 85°C Min. 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1 20 75 -75 0.9 1.35 1.65 2.9 4.4 5.4 2.4 3.7 4.7 0.1 0.1 0.1 0.5 0.5 0.5 ±1 40 50 -50 µA µA mA mA V V Max. -55 to 125°C Min. 2.1 3.15 3.85 0.9 1.35 1.65 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
V
VOH
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
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74AC74
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 3.3 5.0
(*)
Value TA = 25°C Min. Typ. 7.0 5.0 6.0 4.5 5.0 4.0 4.0 3.0 2.0 2.0 1.0 1.0 100 140 1.5 1.5 -0.2 -0.2 0.2 0.2 -1.0 -0.7 300 300 Max. 14.0 10.0 12.0 9.5 7.0 5.0 4.0 3.0 3.0 3.0 1.0 1.0 90 130 -40 to 85°C Min. Max. 16.0 10.5 13.5 10.5 7.0 5.0 4.0 3.0 3.0 3.0 1.0 1.0 90 130 ns -55 to 125°C Min. Max. 17.5 12.0 14.0 10.5 ns ns Unit
tPLH tPHL Propagation Delay Time CK to Q or Q tPLH tPHL Propagation Delay Time PR or CLR to Q or Q tW Pulse Width HIGH or LOW, CK or PR or CLR ts Setup Time D to CK HIGH or LOW th tREM fMAX Hold Time D to CK HIGH or LOW Removal Time PR or CLR to CK Maximum Clock Frequency
(**)
3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 5.0
(**)
ns
ns ns
3.3(*) 5.0(**) 3.3(*) 5.0
(**)
MHz
(*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V
CA PACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 5.0 fIN = 10MHz 35 pF TA = 25°C Min. Typ. 3 Max. Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per Flip-Flop)
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