|
|
Part: 74LVQ245MTR
Category:
Logic
-> LVQ->HCMOS->Low Voltage
Description: Low Voltage Octal Bus Transceiver (3-STATE)
Company: ST Microelectronics, Inc.
Datasheet: Download 74LVQ245MTR datasheet File size : 143 kB
Request For quote: Find where to buy 74LVQ245MTR
Datasheet text preview:
74LVQ245
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER WITH (3-STATE)
s
s s
s
s
s
s s
s
s
s
H IGH SPEED: tPD = 5.7 ns (TYP.) at VCC = 3.3 V C OMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 5 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.5V (TYP.) at VCC = 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245 IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
ORDER CODES
PACKAGE SOP TSSOP TUBE 74LVQ245M T&R 74LVQ245MTR 74LVQ245TTR
DESCRIPTION The 74LVQ245 is a low voltage CMOS OCTAL BUS TRANSCEIVER (3-STATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.
This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. All floating bus terminals during High Impedance State must be held HIGH or LOW.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/9
74LVQ245
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 3, 4, 5, 6, 7, 8,9 18, 17, 16, 15, 14, 13, 12, 11 19 10 20 SYMBOL DIR A1 to A8 B1 to B8 NAME AND FUNCTION Directional Control Data Inputs/Outputs Data Inputs/Outputs
G GND V CC
Output Enable Input Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS G L L H
X : Don`t Care Z : High Impedance
FUNCTION OUTPUT DIR L H X A BUS OUTPUT INPUT Z B BUS INPUT OUTPUT Z A=B B=A Z
ABSOLUTE MAXIMUM RATINGS
Symbol V CC VI VI/O IIK IOK IO Supply Voltage DC Bus I/O Voltage (DIR , G) DC Bus I/O Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA °C °C
ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage (DIR , G) DC Bus I/O Voltage Operating Temperature Input Rise and Fall Time VCC = 3.0V (note 2) Parameter Value 2 to 3.6 0 to VCC 0 to VCC -55 to 125 0 to 10 Unit V V V °C ns/V
1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V
2/9
74LVQ245
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) TA = 25°C Min. 2.0 0.8 IO=-50 µA 3.0 IO=-12 mA IO=-24 mA VOL Low Level Output Voltage IO=50 µA 3.0 IO=12 mA IO=24 mA II Ioz Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 3.6 3.6 3.6 3.6 VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min ± 0.1 ± 0.3 4 36 -25 0.002 0 0.1 0.36 2.9 2.58 2.99 2.9 2.48 2.2 0.1 0.44 0.55 ±1 ±3 40 25 -25 Typ. Max. Value -40 to 85°C Min. 2.0 0.8 2.9 2.48 2.2 0.1 0.44 0.55 ±1 ± 10 40 µA µA µA mA mA V V Max. -55 to 125°C Min. 2.0 0.8 Max. V V Unit
VIH VIL VOH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
3.0 to 3.6
ICC IOLD IOHD
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 3.3 CL = 50 pF 3.3 0.8 V TA = 25°C Min. Typ. 0.5 -0.8 2 -0.5 Max. 0.8 V V Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit
VOLP VOLV VIHD
VILD
Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3)
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
3/9
74LVQ245
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 2.7 3.3 2.7
(*)
Value TA = 25°C Min. Typ. 6.7 5.7 9.3 7.5 7.5 6.6 0.5 0.5 Max. 11.0 9.0 15.0 12.0 12.0 10.0 1.0 1.0 -40 to 85°C Min. Max. 13.0 10.5 17.5 14.0 14.0 11.5 1.0 1.0 -55 to 125°C Min. Max. 15.0 12.0 20.0 16.0 16.0 13.0 1.0 1.0 ns ns ns Unit
tPLH tPHL Propagation Delay Time tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time tOSLH tOSHL Output To Output Skew Time (note1, 2)
3.3(*) 2.7 3.3(*) 2.7 3.3
(*)
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, t OSHL = |tPHLm - t PHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V
CA PACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 3.3 3.3 fIN = 10MHz TA = 25°C Min. Typ. 5 10 20 Max. Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. pF pF pF Unit
CIN CI/O CPD
Input Capacitance I/O Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/8 (per circuit)
4/9
74LVQ245
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open 2VCC Open
W AVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
5/9
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
