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Part: 74LVQ273TTR
Category:
Logic
-> LVQ->HCMOS->Low Voltage
Description: Octal D-type Flip Flop With Clear
Company: ST Microelectronics, Inc.
Datasheet: Download 74LVQ273TTR datasheet File size : 143 kB
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Datasheet text preview:
74LVQ273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
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H IGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3 V C OMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.4V (TYP.) at VCC = 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
ORDER CODES
PACKAGE SOP TSSOP TUBE 74LVQ273M T&R 74LVQ273MTR 74LVQ273TTR
DESCRIPTION The 74LVQ273 is a low voltage CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the CLOCK pulse. W hen the CLEAR input is held low, the Q outputs are held low independently of the other inputs. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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74LVQ273
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL CLEAR Q0 to Q7 D0 to D7 CLOCK GND VC C NAME AND FUNCTION Asynchronous Master Reset (Active LOW) Flip-Flop Outputs Data Inputs Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS CLEAR L H H H
X : Don't Care
OUTPUT FUNCTION CLOCK X Q L L H Qn NO CHANGE CLEAR
D X L H X
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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74LVQ273
AB SOLUTE MAXIMUM RATINGS
Symbol V CC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA °C °C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.0V (note 2) Parameter Value 2 to 3.6 0 to VCC 0 to VCC -55 to 125 0 to 10 Unit V V V °C ns/V
1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) TA = 25°C Min. 2.0 0.8 IO=-50 µA 3.0 IO=-12 mA IO=-24 mA VOL Low Level Output Voltage IO=50 µA 3.0 IO=12 mA IO=24 mA II ICC IOLD IOHD Input Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 3.6 3.6 3.6 VI = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min ± 0.1 4 36 -25 0.002 0 0.1 0.36 2.9 2.58 2.99 2.9 2.48 2.2 0.1 0.44 0.55 ±1 40 36 -25 Typ. Max. Value -40 to 85°C Min. 2.0 0.8 2.9 2.48 2.2 0.1 0.44 0.55 ±1 40 µA µA mA mA V V Max. -55 to 125°C Min. 2.0 0.8 Max. V V Unit
VIH VIL VOH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
3.0 to 3.6
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75
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74LVQ273
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 3.3 CL = 50 pF 3.3 0.8 V TA = 25°C Min. Typ. 0.4 -0.8 2 -0.5 Max. 0.8 V V Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit
VOLP VOLV VIHD
VILD
Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3)
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 , Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 2.7 3.3 2.7 3.3 2.7
(*)
Value TA = 25°C Min. Typ. 7.3 6.0 9.8 8.6 5.0 4.0 5.0 4.0 4.0 3.0 3.0 2.0 4.0 3.0 60 90 2.5 2.2 2.0 1.6 -0.4 -0.3 0.4 0.3 -0.1 0.0 150 190 0.5 0.5 1.0 1.0 Max. 12.0 9.0 15.5 12.5 5.0 4.0 5.0 4.0 4.0 3.0 3.0 2.0 4.0 3.0 50 70 1.0 1.0 -40 to 85°C Min. Max. 14.0 10.5 18.0 14.5 5.0 4.0 5.0 4.0 5.0 4.0 3.5 2.5 4.5 3.5 50 70 1.0 1.0 -55 to 125°C Min. Max. 16.0 12.0 21.0 16.5 ns ns ns ns ns ns ns MHz Unit
tPLH tPHL Propagation Delay Time CK to Q tPHL tW tW ts th tREM fMAX tOSLH tOSHL Propagation Delay Time CLR to Q CLEAR Pulse Width CLOCK Pulse Width Setup Time D to CK, HIGH or LOW Hold Time D to CK, HIGH or LOW Recovery Time CLEAR to CLOCK Maximum Clock Frequency Output To Output Skew Time (note1, 2)
(*)
3.3(*) 2.7 3.3(*) 2.7 3.3 2.7
(*)
3.3 2.7 2.7
(*)
3.3(*) 3.3(*) 2.7 3.3(*)
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, t OSHL = |tPHLm - t PHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V
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74LVQ273
CA PACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 3.3 fIN = 10MHz TA = 25°C Min. Typ. 5 30 Max. Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. pF pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip Flop)
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
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