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Details, datasheet, quote on part number:74LVX16373
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| Part: | 74LVX16373 |
| Category: | Logic => LVX->HCMOS, 5V Input Tolerant->Low Voltage, Low No |
| Description: | Low Voltage CMOS 16-BIT D-type Latch (3-STATE) With 5V Tolerant Input |
| Company: | ST Microelectronics, Inc. |
| Datasheet: | Download 74LVX16373 datasheet File size : 284 kB |
| Request For quote: | Find where to buy 74LVX16373
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Datasheet text preview:
74LVX16373
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE) WITH 5V TOLERANT INPUTS
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H IGH SPEED : tPD = 5.4 ns (MAX.) at VCC = 3V 5V TOLERANT INPUTS POWER DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C L OW N OI S E : VOLP = 0.3V (TYP.) at VCC =3.3V SYMMETRICAL OUTPUT IMPED ANCE: |IOH| = IOL = 4 mA (MIN) at VCC =3V BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUN CTION COMPATIBLE WITH 74 SERIES 16373 IMPROVED LATC H-U P IMMUNITY
TSSOP
O RDE R CO DE S
PACKAGE TSSOP TUBE T&R 74LVX16373TTR
PIN CONNECTION
DESCRIPTION The 74LVX16373 is a low voltage CMOS 16 BIT D-TYPE LATCH with 3 STATE OU TPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and tw o output enable inputs(OE). W hile the nLE input is held at a high level, the nQ outputs will follow the data input precisely. W hen the nLE is taken LOW, the nQ outputs will be latched precisely at the logic level of D input data. W hile the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped w ith protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
February 2003 1/10
74LVX16373
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 1 SYMBOL 1OE NAME AND FUNCTION
IEC LOGIC SYMBOLS
3 State Output Enable Input (Active LOW) 2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 24 2OE 3 State Output Enable Input (Active LOW) 25 2LE Latch Enable Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1LE Latch Enable Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage
TRUTH TABLE
INPUTS OE H L L L LE X L H H D X X L H OUTPUT Q Z NO CHANGE * L H
X : Don`t Care Z : High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level.
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74LVX16373
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
AB SOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 50 -65 to +150 300 Unit V V V mA mA mA mA °C °C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. F unctional operation under these conditions is not implied
RECOMMENDED OPERA TING CONDITIONS
Symbol VCC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 2) (VCC = 3V) Parameter Value 2 to 3.6 0 to 5.5 0 to VCC -55 to 125 0 to 100 Unit V V V °C ns/V
1) Truth T able guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2.0V
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74LVX16373
DC SPEC IFICATIONS
Test Condition Symbol Parameter V CC (V) 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 VOL Low Level Output Voltage 2.0 3.0 3.0 IOZ High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current 3.6 3.6 3.6 IO=-50 µA IO=-50 µA IO=-4 mA IO=50 µA IO=50 µA IO=4 mA VI = VIH or VIL VO = VCC or GND VI = 5V or GND VI = VCC or GND TA = 25°C Min. 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 ±0.25 ± 0.1 4 2.0 3.0 1.9 2.9 2.48 0.1 0.1 0.44 ± 2.5 ±1 40 Typ. Max. Value -40 to 85°C Min. 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.4 0.1 0.1 0.55 ± 2.5 ±1 40 µA µA µA V V Max. -55 to 125°C Min. 1.5 2.0 2.4 0.5 0.8 0.8 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
V
VO H
II ICC
DYNAMIC SWITCH ING CHARA CTERISTICS
Test Condition Symbol Parameter V CC (V) 3.3 TA = 25°C Min. Typ. 0.3 -0.8 CL = 50 pF 2.0 -0.3 V Max. 0.8 Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit
VOLP VOLV VIHD
VILD
Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3)
3.3
3.3
0.8
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V ILD), 0V to threshold (VIHD), f=1MHz.
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74LVX16373
AC ELECTRICAL C HARACTERISTICS (Input tr = tf = 3ns)
Test Condition Symbol Parameter V CC (V) 2.7 2.7 3.3 tPLH tPHL Propagation Delay Time Dn to Qn
(*)
Value TA = 25°C Min. Typ. 7 9 5.5 7 8 9.5 5.4 7.5 7 9.5 5.2 7.6 9 7.7 6 5 4.5 4 1.5 1 0.5 0.5 1.0 1.0 Max. 14 15.5 13 14.5 14 15 13 14 14.9 16 13 14.9 17 15.5 -40 to 85°C Min. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 5 4.5 4 1.5 1 1.5 1.5 Max. 16 17 15 16.5 16 17 15 16 16 17 15 16 18 17 -55 to 125°C Min. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 5 4.5 4 1.5 1 1.5 1.5 ns Max. 16 17 15 16.5 16 17 15 16.5 16 17 15 16 18 17 ns ns ns ns ns ns ns Unit
CL (pF) 15 50 15 50 15 50 15 50 15 50 15 50 50 50 50 50 50 50 50 50 50 50
tPLH tPHL
Propagation Delay Time LE to Qn
3.3(*) 2.7 2.7 3.3(*) t P ZL tPZH Output Enable Time 3.3(*) 2.7 2.7 3.3(*) tPLZ tPHZ tW tS th tOSLH tOSHL 3.3(*) 2.7 3.3 2.7 3.3 2.7 3.3 2.7
(*)
Output Disable Time LE pulse Width, HIGH Setup Time Dn to LE HIGH or LOW Hold Time Dn to LE HIGH or LOW Output to Output Skew Time (note 1,2)
(*)
(*)
3.3(*) 2.7 3.3
(*)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V
CA PACITIVE CHARA CTERISTICS
Test Condition Symbol Parameter V CC (V) TA = 25°C Min. Typ. 2.5 4 3.0 fIN = 10MHz 17 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF pF Unit
CIN C O UT CPD
Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
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