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Details, datasheet, quote on part number:74VHC374TTR
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Datasheet text preview:
74VHC374
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING
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H IGH SPEED: fMAX = 270 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C H IGH NOISE IMMUNITY: VNIH = V NIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.)
SOP
TSSOP
ORDER CODES
PACKAGE SOP TSSOP TUBE 74VHC374M T&R 74VHC374MTR 74VHC374TTR
DESCRIPTION The 74VHC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. PIN CONNECTION AND IEC LOGIC SYMBOLS
W hile the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The Output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
June 2001
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74VHC374
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 D0 to D7 CK GND VC C NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 3-State Outputs Data Inputs Clock Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS OE H L L L
X : Don't Care Z : High Impedance
OUTPUT D X X L H Q Z NO CHANGE L H
CK X
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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74VHC374
AB SOLUTE MAXIMUM RATINGS
Symbol V CC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 75 -65 to +150 300 Unit V V V mA mA mA mA °C °C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) (VCC = 5.0 ± 0.5V) Parameter Value 2 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 100 0 to 20 Unit V V V °C ns/V
1) VIN from 30% to 70% of V CC
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74VHC374
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low Level Output Voltage 2.0 3.0 4.5 3.0 4.5 Ioz High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current 5.5 0 to 5.5 5.5 IO=-50 µA IO=-50 µA IO=-50 µA IO=-4 mA IO=-8 mA IO=50 µA IO=50 µA IO=50 µA IO=4 mA IO=8 mA VI = VIH or VIL VO = VCC or GND VI = 5.5V or GND VI = VCC or GND TA = 25°C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 ±0.25 ± 0.1 4 2.0 3.0 4.5 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 ± 2.5 ±1 40 Typ. Max. Value -40 to 85°C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.4 3.7 0.1 0.1 0.1 0.55 0.55 ± 2.5 ±1 40 µA µA µA V V Max. -55 to 125°C Min. 1.5 0.7VCC 0.5 0.3VCC V V Max. Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
VOH
II ICC
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74VHC374
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 3.3(*) 3.3 5.0 tP Z L tPZH Output Enable Time
(*) (**)
Value TA = 25°C Min. Typ. 8.1 10.6 5.4 6.9 Max. 12.7 16.2 8.1 10.1 11.0 14.5 7.6 9.6 14.0 8.8 5.0 5.0 4.5 3.0 2.0 2.0 60 100 250 270 1.5 1.0 60 100 1.5 1.0 -40 to 85°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 15.0 18.5 9.5 11.5 13.0 16.5 9.0 11.0 16.0 10.0 5.5 5.0 4.5 3.0 2.0 2.0 60 100 1.5 1.0 -55 to 125°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 15.0 18.5 9.5 11.5 13.0 16.5 9.0 11.0 16.0 10.0 5.5 5.0 4.5 3.0 2.0 2.0 ns ns ns Unit
CL (pF) 15 50 15 50 15 50 15 50 15 50 RL = 1K RL = 1K RL = 1K RL = 1K RL = 1K RL = 1K
tPLH tPHL
Propagation Delay Time CK to Q
5.0(**) 3.3(*) 3.3 5.0 tPLZ tPHZ tw ts th fMAX tOSLH tOSHL Output Disable Time Clock Pulse Width HIGH or LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Maximum Clock Frequency Output to Output Skew time (note 1)
(*) (**)
7.1 9.6 5.1 6.6 10.2 6.1
5.0(**) 3.3(*) 3.3(*) 3.3(*) 5.0
(**)
ns
3.3(*) 5.0(**) 3.3(*) 5.0
(**)
ns ns
3.3(*) 5.0(**) 3.3(*) 5.0(**) 50 50
MHz ns
(*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V Note 1 : Parameter guaranteed by design. tsoLH = |t pLHm - t pLHn|, t soHL = |tpHLm - tpHLn |
CA PACITIVE CHARACTERISTICS
Test Condition Symbol Parameter Min. CIN CO U T CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) TA = 25°C Typ. 7 9 32 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF pF Unit
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip-Flop)
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