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Details, datasheet, quote on part number:74VHCT138AM
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Datasheet text preview:
74VHCT138A
3 TO 8 LINE DECODER (INVERTING)
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H IGH SPEED: tPD = 7.6 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C C OMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (MAX.)
SOP
TSSOP
ORDER CODES
PACKAGE SOP TSSOP TUBE 74VHCT138AM T&R 74VHCT138AMTR 74VHCT138ATTR
DESCRIPTION The 74VHCT138A is an advanced high-speed CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. When enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high. PIN CONNECTION AND IEC LOGIC SYMBOLS
The three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
June 2001
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74VHCT138A
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 2, 3 4, 5 6 15, 14, 13, 12, 11, 10, 9, 7 8 16 SYMBOL A, B, C G2A, G2B G1 Y0 to Y7 NAME AND FUNCTION Address Inputs Enable Inputs Enable Input Outputs
GND V CC
Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS OUTPUTS ENABLE G2B X X H L L L L L L L L G2A X H X L L L L L L L L G1 L X X H H H H H H H H C X X X L L L L H H H H SELECT B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L
X : Don't Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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74VHCT138A
AB SOLUTE MAXIMUM RATINGS
Symbol V CC VI VO VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 50 -65 to +150 300 Unit V V V V mA mA mA mA °C °C
ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) VCC = 0V 2) High or Low State
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (VCC = 5.0 ± 0.5V) Parameter Value 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 20 Unit V V V V °C ns/V
1) VCC = 0V 2) High or Low State 3) VIN from 0.8V to 2V
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74VHCT138A
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 0 IO=-50 µA IO=-8 mA IO=50 µA IO=8 mA VI = 5.5V or GND VI = VCC or GND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V TA = 25°C Min. 2 0.8 4.4 3.94 0.0 0.1 0.36 ± 0.1 4 1.35 0.5 4.5 4.4 3.8 0.1 0.44 ± 1.0 40 1.5 5.0 Typ. Max. Value -40 to 85°C Min. 2 0.8 4.4 3.7 0.1 0.55 ± 1.0 40 1.5 5.0 Max. -55 to 125°C Min. 2 0.8 Max. V V V V µA µA mA µA Unit
VIH VIL VOH VOL II ICC
High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Output Leakage Current
IC C
IOPD
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test Condition Symbol Parameter VC C (V) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0
(*)
Value TA = 25°C Min. Typ. 7.6 8.1 6.6 7.1 7.0 7.5 Max. 10.4 11.4 9.1 10.1 9.6 10.6 -40 to 85°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 Max. 12.0 13.0 10.5 11.5 11.0 12.0 -55 to 125°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 Max. 12.0 13.0 10.5 11.5 11.0 12.0 ns ns ns Unit
CL (pF) 15 50 15 50 15 50
tPLH tPHL tPLH tPHL tPLH tPHL
Propagation Delay Time A, B, C, to Y Propagation Delay Time G1 to Y Propagation Delay Time G2A, G2B to Y
(*) Voltage range is 5.0V ± 0.5V
CA PACITIVE CHARACTERISTICS
Test Condition Symbol Parameter Min. CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) TA = 25°C Typ. 6 36 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF Unit
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
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74VHCT138A
TEST CIRCUIT
CL =15/50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
W AVEFORM 1 : PROPAGATION DELAYS FOR INVERTING OUTPUTS(f=1MHz; 50% duty cycle)
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