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Details, datasheet, quote on part number:74VHCT574AT
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Datasheet text preview:
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74VHCT574A
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
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HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY LOW NOISE VOLP = 0.9V (Max.)
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74VHCT574AM 74VHCT574AT outputs will be set to logic states that were setup at the D inputs. While t he OE input is low, the 8 outputs will be in a normal logic state (high or low logic level) and, while high level, the outputs will be in a high impedance state. The output control does not affect the internal operation of f lip flop; that is, the old data can be retained or the new data can be entered even while t he output s are off. Power down protection is provided on all inputs and outputs and 0 t o 7V can be accepted on inputs with no regard to the supply voltage. This device can be used t o interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The 74VHCT574A is an advanced high-speed CMOS OCTAL D-TYPE FLIP F LOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and d ouble-layer metal wiring C2MOS technolo gy. This 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q
PIN CONNECTION AND IEC L OGIC SYMBOLS
August 1999
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74VHCT574A
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
P I N No 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 S Y M B OL OE D0 to D7 NA M E AND F U NCT I O N 3 St ate Out put Enable In put (Act iv e LOW ) D ata I nputs
Q0 to Q7
3 St ate Out puts
C LOCK GND VCC
C lock I nput ( LOW to H IGH , edge t riggere d) Gr ound ( 0V ) Po si tive S upply Volta ge
TRUTH TABLE
I N P UT S OE H L L L
X: Don't Care Z: High Impedance
O U T PU T S D X X L H Q Z N O CHANGE L H
CK X
LOGIC DIAGRAM
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74VHCT574A
ABSOLUTE MAXIMUM RATINGS
S ym b o l VC C VI VO VO IIK IOK IO Tstg TL Su pply V o ltage D C Input Volta ge D C Outp ut Volt age (s ee note 1) D C Outp ut Volt age (s ee note 2) D C Input Diode Curre nt D C Outp ut Diode C urrent D C Outp ut Current St or age Tem perat ur e Lead T e mperat ure (10 s ec) P ara met er V al u e -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 50 -65 to +150 300 Unit V V V V mA mA mA mA
o o
ICC or IGND D C VCC o r Gro und Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) Output in OFF State 2) High or Low State
RECOMMENDED OPERATING CONDITIONS
S ym b o l VC C VI VO VO Top dt/dv S upply Vo ltage I nput V oltage O ut put Volt age ( see note 1) O ut put Volt age ( see note 2) O perati ng T em peratur e I nput R is e a nd F all T im e (se e note 3) (V CC = 5.0 ± 0.5 V) P ara met er V al u e 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -40 to +85 0 to 20 Uni t V V V V
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C
ns/V
1) Output in OFF State 2) High or Low State 3)VIN from 0.8V to 2 V
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74VHCT574A
DC SPECIFICATIONS
S ymb o l P ara met er T est C o n d i t i o n s V CC ( V) VI H VIL VOH VOL IOZ High Level In put Volt age Low Level I nput Volt age High Level Ou t put Volt age Low Level O utp ut Volt age High Im pedance Out put Leaka ge Current Input L eakage Current Quiesce nt Su pply Current Additional W o rst C as e Supply Current Out put Leaka ge Current 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 4.5 to 5.5 I O = - 50 µ A IO=-8 m A I O= 50 µ A IO=8 mA VI = VIH or VIL VO = 0V to 5.5V VI = 5.5V or GND VI = VCC or GND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V 4.4 3.94 0.0 0.1 0.36 ±0.25 4.5 M in. 2 0.8 4.4 3.8 0.1 0.44 ±2.5 T yp . V al u e T A = 25 o C M ax . - 40 t o 85 o C M in . 2 0.8 M ax . V V Un i t
V V µA
II ICC ICC
0 to 5.5 5.5 5.5
±0.1 4 1.35
±1.0 40 1.5
µA µA mA
IOPD
0
0.5
5.0
µA
AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns)
S ymb o l P ara met er V CC ( V) tPL H tPHL tPZL tPZH tPLZ tPHZ fMAX tOSLH tOSHL Propagatio n Delay Tim e C K to Q Out put EnableTim e Out put Disable T ime Max im um C lock Fre quency Out put to Ou tp ut S kew Tim e (n ote 1) T est Co n d i t i o n CL (p F ) 15 50 15 50 50 15 50 50 RL=1K RL=1K 90 85 V al u e T A = 25 o C M i n . T yp . M ax . 4.1 5.6 6.5 7.3 7.0 140 130 1.5 9.4 10.4 10.2 11.2 11.2 Un i t - 40 t o 85 o C M i n . M ax . 1.0 1.0 1.0 1.0 1.0 80 1.5 10.5 11.5 11.5 12.5 12.0 ns ns ns M Hz ns
5.0 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*)
(*)
(*) Voltage range is 5V ± 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm- tpLHn|, tsoHL = |tpHLm - tpHLn|
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74VHCT574A
CAPACITIVE CHARACTERISTICS
S ymb o l P ara met er T est C o n d i t i o n s M in. C IN COUT CPD Input C apacita nce Out put Capac itance Power D iss ipation Capacit ance (n ot e 1) T yp . 4 9 25 V al u e T A = 25 o C M ax . 10 - 40 t o 85 o C M in . M ax . 10 pF pF pF Un i t
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD · VCC · fIN + ICC/8 (per Flip-Flop)
DYNAMIC SWITCHING CHARACTERISTICS
S ymb o l P ara met er T est C o n d i t i o n s V CC ( V) VOLP VOLV VIHD VIL D Dynamic Low V oltage Quiet Out put (not e 1 , 2) Dynamic High Vo ltage Input ( note 1, 3) Dynamic Low V oltage Input ( note 1, 3) 5.0 -1.6 5.0 5.0 C L = 50 pF 3.5 1.5
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V al u e T A = 25 C M in. T yp . 1.2 -1.2 M ax . 1.6 - 40 t o 85 C M in . M ax .
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Un i t
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1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
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