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Details, datasheet, quote on part number:ESDA6V1-5W6
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Datasheet text preview:
®
Application Specific Discretes
A.S.D.ä
TRANSILTM ARRAY FOR ESD PROTECTION
ESDA6V1-5W6
APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : n Computers n Printers n Communication systems n Cellular phone handsets and accessories n Other telephone sets n Set top boxes DESCRIPTION The ESDA6V1-5W6 is a 5-bit wide monolithic suppressor which is designed to protect components connected to data and transmission lines against ESD.
SOT323-6L
FUNCTIONAL DIAGRAM
I/O1
FEATURES
n n n n
I/O5 I/O4
5 UNIDIRECTIONAL TRANSILTM FUNCTIONS BREAKDOWN VOLTAGE: VBR = 6.1V min LOW LEAKAGE CURRENT: IR max < 1 µA VERY SMALL SIZE FOR PCB SPACE SAVING: 4.2mm2 TYPICALLY
Gnd
I/O2
I/O3
BENEFITS
n n
High integration Suitable for high density boards
ESD response to IEC61000-4-2 (air discharge 16kV, positive surge)
COMPLIES WITH THE FOLLOWING STANDARDS: - IEC 61000-4-2: level 4 15 kV (air discharge) 8 kV (contact discharge) - MIL STD 883C-Method 3015-6: class3 (human body model)
March 2000 - Ed: 1A
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ESDA6V1-5W6
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol VPP Test conditions ESD discharge - MIL STD 883C - Method 3015-6 IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge Peak pulse power (8/20µs) Junction temperature Storage temperature range Lead solder temperature (10 seconds duration) Operating temperature range (note 1) Value 25 20 15 100 150 -55 to +150 260 -40 to +125 Unit kV
PPP Tj Tstg TL Top
W °C °C °C °C
Note 1: The evolution of the operating parameters versus temperature is given by curves and T parameter.
ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol VRM VBR VCL IRM IPP T C Rd VF Parameter
I
Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Capacitance Dynamic impedance Forward voltage drop
Slope = 1/Rd
IF
VBR Vcl VRM IRM
VF V
IPP
VBR @ IR min. Type max .
IRM @ VRM max.
Rd typ. note 2
T max. note 3 10-4/°C 6
C typ. 0V bias pF 50
VF @ IF max
V ESDA6V1-5W6 6.1
V 7.2
mA 1
µA 1
V 3
m 610
V 1.25
mA 200
Note 2 : Square pulse, Ipp = 15A, tp=2.5µs. Note 3: VBR = T * (Tamb - 25°C) * VBR (25°C)
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Fig. 1: Peak power dissipation versus initial junction temperature.
Ppp[Tj initial]/Ppp[Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
1000
Fig. 2: Peak pulse power versus exponential pulse duration (Tj initial = 25°C).
Ppp(W)
100
Tj initial(°C) 0 25 50 75 100 125 150 175
10 1
tp(µs)
10 100
Fig. 3: Clamping voltage versus peak pulse current (Tj initial = 25°C) Rectangular waveform tp = 2.5µs.
Fig. 4: Capacitance versus reverse applied voltage (typical values).
Ipp(A)
50.0
tp=2.5µs
C(pF)
50 40 30
F=1MHz Vosc=30mV
10.0
1.0
20
Vcl(V)
0.1 0 5 10 15 20 25 30 35 40
10 0.5 1.0 1.5 2.0
VR(V)
2.5 3.0 3.5 4.0 4.5 5.0
Fig. 5: Relative variation of leakage current versus junction temperature (typical values).
Fig. 6: Peak forward voltage drop versus peak forward current (typical values).
IR[Tj] / IR[Tj=25°C]
50
IFM(A)
1E+0
Tj=25°C
10
1E-1
1E-2
Tj(°C)
1 25 50 75 100 125
VFM(V) 1E-3 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
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APPLICATION EXAMPLE
Implementation of ESDA6V1-5W6 in a typical application
TECHNICAL INFORMATION ESD PROTECTION The ESDA6V1-5W6 is particularly optimized to perform ESD protection. ESD protection is achieved by clamping the unwanted overvoltage. The clamping voltage is given by the following formula :
Vcl = Vbr + Rd Ipp
As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor.
Fig. A1: ESD clamping behavior
Rg
Rd
IC to be protected
Connector
Vg
Vbr
Voutput
Rload
Device to be protected
ESD Surge
ESDA6V1-5W6
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To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis : Rg > Rd and Rload > Rd we have:
Vin = Vbr + Rd ×
Vg Rg
The results of the calculation done for Vg = 8 kV, Rg = 330 (IEC 61000-4-2 standard), Vbr = 6.4 V (typ.) and Rd = 0.61 (typ.) give: Vouput = 21.2 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side.
Fig. A2: Measurement conditions:
ESD SURGE 16kV Air Discharge
TEST BOARD
E62
Vi/o
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