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Details, datasheet, quote on part number:ESDA6V1U1
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| Part: | ESDA6V1U1 |
| Category: | Power Management => Protection and Isolation => ESD Suppression |
| Description: | Transil Array For Esd Protection - (ASD) |
| Company: | ST Microelectronics, Inc. |
| Datasheet: | Download ESDA6V1U1 datasheet File size : 146 kB |
| Request For quote: | Find where to buy ESDA6V1U1
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Datasheet text preview:
ESDA6V1U1
Application Specific Discretes A.S.D.
TRANSIL ARRAY FOR ESD PROTECTION
APPLICATIONS Where transient over voltage protection in ESD sensitive equipment is required, such as : COMPUTERS PRINTERS COMMUNICATION SYSTEMS GSM HANDSETS AND ACCESSORIES CAR RADIO It is par ticular y recommended for parallel por t protection where the line interface withstands only 2 kV ESD surge.
s s s s s
SO-8
FEATURES
s s
s
6 UNIDIRECTIONAL TRANSIL FUNCTIONS LOW LEAKAGE CURRENT: IR max. < 2 µA 200 W PEAK PULSE POWER (8/20 µs)
FUNCTIONAL DIAGRAM
DESCRITION The ESDA6V1U1 is a monolithic voltage suppressor designed to protect components which are connected to data and transmission lines against ESD. It clamps the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transients. BENEFITS High ESD protection level : up to 25 kV High integration Suitable for high density boards COMPLIES WITH THE FOLLOWING STANDARDS : IEC61000-4-2 : level 4 MIL STD 883C-Method 3015-6 : class3 (human body model)
August 2002 - Ed: 3A
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ESDA6V1U1
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol VPP PPP Tstg Tj TL Parameter Electrostatic discharge MIL STD 883C - Method 3015-6 Peak pulse power (8/20µs) Storage temperature range Maximum junction temperature Maximum lead temperature for soldering during 10s Value 25 200 - 55 to + 150 125 260 Unit kV W °C °C
°C
ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol VRM VBR VCL IRM IPP Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Capacitance Dynamic resistance Forward voltage drop
T
C Rd VF
Types min.
VBR @ max.
IR
IRM @ VRM max.
Rd typ. note 1
T max. note 2 10 /°C 6
-4
C typ. 0V bias pF 100
VF @ max.
IF
V ESDA6V1U1 6.1
V 7.2
mA 1
µA 2
V 5
0.5
V 1.5
mA 200
note 1 : Square pulse, Ipp = 25A, tp=2.5µs. note 2 : VBR = T* (Tamb -25°C) * VBR (25°C)
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ESDA6V1U1
CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: VCL = VBR + Rd IPP Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The shor t duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20µs and 10/1000µs surges. As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd.
2.5µs duration measurement wave.
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ESDA6V1U1
Fig. 1 : Peak power dissipation versus initial junction temperature. Fig. 2 : Peak pulse power versus exponential pulse duration (Tj initial = 25 °C).
Fig. 3 : Clamping voltage versus peak pulse current (Tj initial = 25 °C). Rectangular waveform tp = 2.5 µs.
Fig. 4 : Capacitance versus reverse applied voltage (typical values).
Fig. 5 : Relative variation of leakage current versus junction temperature (typical values).
Fig. 6 : Peak forward voltage drop versus peak forward current (typical values).
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APPLICATION EXAMPLE : Protection of logic-level signals.
APPLICATION EXAMPLE : Protection of symmetrical signals. Note : Capacitance value between any I/O pin and Ground is divided by 2.
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