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Details, datasheet, quote on part number:ESDA6V1W5
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| Part: | ESDA6V1W5 |
| Category: | Power Management => Protection and Isolation => ESD Suppression |
| Description: | Qual Transil Array For Esd Protection |
| Company: | ST Microelectronics, Inc. |
| Datasheet: | Download ESDA6V1W5 datasheet File size : 62 kB |
| Request For quote: | Find where to buy ESDA6V1W5
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Datasheet text preview:
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ESDA6V1W5
QUAL TRANSILTM ARRAY FOR ESD PROTECTION
Application Specific Discretes A.S.D.TM
MAIN APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : Computers Printers Communication systems GSM handsets and accessories Other telephone sets Set top boxes FEATURES 4 unidirectional TRANSIL TM functions. Breakdown voltage : VBR = 6.1 V min. Low leakage current : < 1µA. Very low PCB space consuming : 4.2 mm2 typically. DESCRIPTION The ESDA6V1W5 is a 4-bit wide monolithic suppressor which is designed to protect component connected to data and transmission lines against ESD. It clamps the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transients.
SOT323-5L FUNCTIONAL DIAGRAM
1
5
2
3
4
BENEFITS High ESD protection level : up to 25 kV. High integration. Suitable for high density boards. COMPLIES WITH THE FOLLOWING STANDARDS : IEC 1000-4-2 level 4 MIL STD 883C-Method 3015-6 : class 3. (human body model) ESD RESPONSE TO IEC1000-4-2 (air discharge 16 kV, positive surge)
September 1999 - Ed: 1A
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ESDA6V1W5
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol VPP Parameter ESD discharge Test conditions MIL STD 883C - Method 3015-6 IEC1000-4-2, air discharge IEC1000-4-2, contact discharge Value 25 16 9 150 - 40 to + 85 150 - 55 to + 150 260 Unit kV
PPP Top Tj Tstg TL
Peak pulse power (8/20 µs) Operating temperature range Junction temperature Storage temperature range Lead solder temperature (10 secondes duration)
W °C °C °C °C
ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol VRM VBR VCL IRM IPP Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Capacitance per line Dynamic resistance Forward voltage drop
slope : 1 / R d VCL VBR VRM IRM IR
I
V
T
C Rd VF
IPP
Types
VBR min.
@ max.
IR
IRM max.
@
VRM
Rd typ. note 1
T max. note 2 10 /°C 6
-4
C typ. 0V bias pF 90
VF @ max.
IF
V
V 7.2
mA 1
µA 1
V 3
m 350
V 1.25
mA 200
ESDA6V1W5
6.1
note 1 : Square pulse Ipp = 15A, tp=2.5µs. note 2 : VBR = T* (Tamb -25°C) * VBR (25°C)
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ESDA6V1W5
CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: VCL = VBR + Rd IPP Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20µs and 10/1000µs surges.
I Ipp
2µs tp = 2.5µs
t
2.5µs duration measurement wave. As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd.
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ESDA6V1W5
Fig. 1 : Peak power dissipation versus initial junction temperature
Ppp[Tj initial]/Ppp[Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
1000
Fig. 2 : Peak pulse power versus exponential pulse duration (Tj initial = 25 °C)
Ppp(W)
100
Tj initial(°C) 0 25 50 75 100 125 150 175
tp(µs) 10 1 10 100
Fig. 3 : Clamping voltage versus peak pulse current (Tj initial = 25 °C). Rectangular waveform tp = 2.5 µs.
Ipp(A) 50.0
tp=2.5µs
Fig. 4 : Capacitance versus reverse applied voltage (typical values).
90 80 70 60 50
C(pF)
F=1MHz Vosc=30mV
10.0
1.0
40 30 20
Vcl(V) 0.1 0 5 10 15 20 25 30
VR(V) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
10 1.0
Fig. 5 : Relative variation of leakage current versus junction temperature (typical values).
IR[Tj] / IR[Tj=25°C] 5 4 3
Fig. 6 : Peak forward voltage drop versus peak forward current (typical values).
IFM(A) 1E+0
Tj=25°C
1E-1
2
1E-2
Tj(°C) 1 25 50 75 100 125 150
1E-3 0.6 0.7 0.8 0.9
VFM(V) 1.0 1.1 1.2 1.3 1.4
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ESDA6V1W5
1. ESD protection by the ESDA6V1W5 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system. Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground.
A Keyboard terminal printer etc B I/O C D FUNCTIONAL DECODER
The ESDA6V1W5 array is the ideal product for use as board level protection of ESD sensitive semiconductor components. The tiny SOT323-5L package makes the ESDA6V1W5 device some of the smallest ESD protection devices available. It also allows design flexibility in the design of "crowded" boards where the space saving is at a premium. This enables to shorten the routing and can contribute to improved ESD performance.
2. Circuit Board Layout Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended : The ESDA6V1W5 should be placed as near as possible to the input terminals or connectors. Minimise the path length between the ESD suppressor and the protected device Minimise all conductive loops, including power and ground loops The ESD transient return path to ground should be kept as short as possible. Use ground planes whenever possible.
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