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Details, datasheet, quote on part number:ESDALC6V1W
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Datasheet text preview:
®
ESDALC6V1W5
QUAD TRANSILTM ARRAY FOR ESD PROTECTION
Application Specific Discretes A.S.D.
MAIN APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : Computers Printers Communication systems and cellular phones Video equipment Set top boxes
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FEATURES 4 unidirectional TRANSILTM functions. ESD Protection: IEC61000-4-2 level 4 Breakdown voltage VBR = 6.1V min Low leakage current < 1µA @ 3 Volts Low capacitance device
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SOT323-5L
FUNCTIONAL DIAGRAM
DESCRIPTION The ESDALC6V1W5 is a 4-bit wide monolithic suppressor which is designed to protect component connected to data and transmission lines against ESD. It clamps the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transients. BENEFITS High ESD protection level : up to 25 kV. Capacitance: 12pF @ 0V Typ. High integration. Suitable for high density boards.
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I/01 GND I/02
I/04
I/03
COMPLIES WITH THE FOLLOWING STANDARDS :
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IEC61000-4-2 level 4: 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883C-Method 3015-6 : class 3. (human body model) 25kV (HBM)
June 2002 - Ed: 4A
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ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol VPP Parameter Test conditions Value ± 25 ± 15 ±8 25 150 - 55 to + 150 - 40 to + 150 Unit kV
ESD discharge - MIL STD 883E - Method 3015-7 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Peak pulse power (8/20 µs) Junction temperature Storage temperature range Operating temperature range
PPP Tj Tstg Top
W °C °C °C
ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol VRM VBR VCL IRM IPP C Rd Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Capacitance per line Dynamic resistance
slope : 1 / Rd IPP VCL VBR VRM IRM IR
I
V
Types min.
VBR
@ max.
IR
IRM max.
@
VRM
Rd typ. note 1
T max. note 2 10 /°C 6
-4
C typ. 3V bias pF 7.5
C max. 3V bias pF 9.5
V
V 7.2
mA 1
µA 1
V 3
m 1100
ESDALC6V1W5
6.1
Note 1 : Square pulse Ipp = 15A, tp=2.5µs. Note 2 : VBR = T* (Tamb -25°C) * VBR (25°C)
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ESDALC6V1W5
Fig. 1: Relative variation of peak pulse power versus initial junction temperature.
Ppp[Tj initial] / Ppp [Tj initial = 25°C]
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 175
Fig. 2: Peak pulse power versus exponential pulse duration.
Ppp(W)
100
Tj initial = 25°C
Tj(°C)
10 1
tp(µs)
10 100
Fig. 3: Junction capacitance versus reverse voltage applied (typical values).
C(pF)
14 12 10 8 6
F=1MHz Vosc =30mVRMS Tj=25°C
Fig. 4: Clamping voltage versus peak pulse current (maximum values, rectangular waveform).
Ipp(A)
100.0
10.0
1.0
4 2
VR(V)
0 0 1 2 3 4 5
Vcl(V)
0.1 0 10 20 30 40
tp=2.5µs Tj initial =25°C
50
60
Fig. 5: Relative variation of leakage current versus junction temperature (typical values).
IR [Tj] / IR [Tj=25°C]
100
Fig. 6: Application example
I/02
Connector
I/01 I/04 I/03
IC to be protected
10
Tj(°C)
1 25 50 75 100 125
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ESDALC6V1W5
TECHNICAL INFORMATION 1. ESD protection by ESDALC6V1W5 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems. As a transient voltage suppressor, ESDALC6V1W5 is an ideal choice for ESD protection by suppressing ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDALC6V1W5. ESDALC6V1W5 serves as a parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the ESDALC6V1W5 becomes a low impedance path diverting the transient current to ground. The clamping voltage is given by the following formula: VCL = VBR + Rd.IPP As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor.
Fig. A1: ESD clamping behavior
RG VG
IPP Rd V(i/o) VBR RL O D A
Device to be protected
ESD surge
ESDALC6V1W5
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis: Rg > Rd and Rload > Rd we have: V V (i / o ) = V BR + Rd × g Rg The results of the calculation done Vg = 8kV, Rg = 330 (IEC61000-4-2 standard), VBR = 6.1V (min) and Rd = 1.1 (typ.) give: V (i / o ) = 32,8Volts This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side.
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Fig. A2: ESD test board Fig. A3: ESD test configuration
TEST BOARD
V (iioo) (// )
I/O1, I/O2, I/O3 or I/O4 ± 8kV ESD Contact discharge B2
V(i/o)
The measurements done here after show very clearly (Fig. A4) the high efficiency of the ESD protection: the clamping voltage V(i/o) becomes very close to +VBR (positive way, Fig. A4a) and -VBR (negative way, Fig. A4b).
Fig. A4: Remaining voltage during ESD surge
V(i/o)
V(i/o)
a: Response in the positive way
b: Response in the negative way
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