COMPLETE CODEC AND FILTERING SYSTEM (DEVICE) INCLUDING: Transmit high-pass and low-pass filtering. Receive low-pass filter with sin x/x correction. Active RC noise filters µ-law or A-law compatible COder and DECoder. Internal precision voltage reference. Serial I/O interface. Internal auto-zero circuitry. A-LAW 16 PINS (ETC5057FN, 20 PINS) µ-LAW WITHOUT SIGNALING, 16 PINS (ETC5054FN, 20 PINS) MEETS OR EXCEEDS ALL D3/D4 AND CCITT SPECIFICATIONS ±5V OPERATION LOW OPERATING POWER - TYPICALLY 60 mW POWER-DOWN STANDBY MODE - TYPICALLY 3 mW AUTOMATIC POWER-DOWN TTL OR CMOS COMPATIBLE DIGITAL INTERFACES MAXIMIZES LINE INTERFACE CARD CIRCUIT DENSITY to 70°C OPERATION DESCRIPTION The ETC5057/ETC5054 family consists of A-law and µlaw monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in the block diagram below, and a serial PCM interface. The devices are fabricated using doublepoly CMOS process. The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded A-law or µlaw PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded A-law or µlaw code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz and is followed by a single-ended power amplifier capable of driving low impedance loads. The devices require 1.536 MHz, 1.544
MHz, or 2.048 MHz transmit and receive master clocks, which may be asynchronous, transmit and receive bit clocks which may vary from 64 kHz to 2.048 MHz, and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats.
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Name VBB GNDA VFRO VCC FSR Pin Type * S GND I N° DIP PLCC and SO Function Negative Power Supply Analog Ground Receive Filter Output Positive Power Supply Receive Frame Sync Pulse Receive Data Input Shift-in Clock VBB All signals are referenced to this pin. Analog Output of the Receive Filter VCC Enables BCLKR to shift PCM data into DR. FSR an 8kHz pulse train. See figures 1, 2 and 3 for timing details. PCM data is shifted into DR following the FSR leading edge. Shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and receive directions (see table 1). This input has an internal pullup. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be but should be asynchronous with MCLKX, synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected continuously high, the device is powered down. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKR. Shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLKX. The TRI-STATE® PCM data output which is enabled by FSX. Enables BCLKX to shift out the PCM data on DX. FSX an 8 kHz pulse train. See figures 1, 2 and 3 for timing details. Open drain output which pulses low during the encoder time slot. Recommended to be grounded if not used. Analog output of the transmit input amplifier. Used to set gain externally. Inverting Input of the Transmit Input Amplifier. Non-inverting Input of the Transmit Input Amplifier. Description
Transmit Master Clock Shift-out Clock Transmit Data Output Transmit Frame Sync Pulse Transmit Time Slot Gain Set Inverting Amplifier Input Non-inverting Amplifier Input
I: Input, O: Output, S: Power Supply Pins 4,10,11 and 13 are not connected TRI-STATE® is a trademark of National Semiconductor Corp.