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Part: HCF40161BEY
Category:
Logic
-> HCF->CMOS 4000B Series
Description: Synchronous Programmable 4-BIT Counters
Company: ST Microelectronics, Inc.
Datasheet: Download HCF40161BEY datasheet File size : 4262 kB
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Datasheet text preview:
HCF40161B
SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR
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INTERNAL LOOK-AHEAD FOR FAST COUNTING C ARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOW-POWER TTL COMPATIBILITY STAND ARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF40161BEY HCF40161BM1 T&R HCF40161M013TR
DESCRIPTION HC F40161B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF40161B is a 4-bit synchronous programmable counter. The CLEAR function is asynchronous. A low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD and ENABLE inputs. A low level at the LOAD inputs disables the counter and causes the output to agree with the set-up data after the following CLOCK pulse regardless of the conditions of the
ENABLE inputs. The carry look-ahead circuitry provides for cascading counter for n-bit synchronous application without additional gating. Counting is enabled when both the PE and TE inputs are high. The TE input is fed forward to enable COUT. This enable output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE and TE inputs may occur when the clock is either high or low.
PIN CONNECTION
September 2002
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HCF40161B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2 3, 4, 5, 6 7 10 9 14, 13, 12, 11 15 8 16 SYMBOL CLEAR CLOCK P1 to P4 PE TE LOAD Q1 to Q4 NAME AND FUNCTION Asynchronous Master Reset Clock Input (LOW to HIGH, Edge-triggered) Data Inputs Count Enable Input Count Enable Carry Input Parallel Enable Input Flip Flop Outputs
CARRY OUT Terminal Count Output VSS Negative Supply Voltage V DD Positive Supply Voltage
LOGIC DIAGRAM
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HCF40161B
TRUTH TABLE
CLOCK CLR H H H H X
(X) : Don't Care NC : No Change
LOAD L H H H X
PE X L X H X
TE X X L H X
OPERATION PRESET NC NC COUNT RESET
L
TIMING DIAGRAM
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