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Part: L6574D
Category:
Power Management
-> Motor Controller/Drivers
-> Power Controllers & Motor Drivers
Description: Cfl/tl Ballast Driver Preheat And Dimming
Company: ST Microelectronics, Inc.
Datasheet: Download L6574D datasheet File size : 1147 kB
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Datasheet text preview:
L6574
CFL/TL BALLAST DRIVER PREHEAT AND DIMMING
s s s
s s s s s s s s s s
HIGH VOLTAGE RAIL UP TO 600V dV/dt IMMUNITY ± 50 V/ns IN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY: 250mA SOURCE 450mA SINK SWITCHING TIMES 80/40ns RISE/FALL WITH 1nF LOAD CMOS SHUT DOWN INPUT UNDER VOLTAGE LOCK OUT PREHEAT AND FREQUENCY SHIFTING TIMING SEN SE OP AMP FOR CLOSED LOOP CONTROL OR PROTECTION FEATURES HIGH ACCURACY CURRENT CONTROLLED OSCILLATOR INTEGRATED BOOTSTRAP DIODE CLAMPING ON VS. SO16, DIP 16 PACKAGES
SO16N
DIP16
ORDERING NUMBERS: L6574D L6574
The device is intended to drive two power MOSFETS, in the classical half bridge topology, ensuring all the features needed to drive and properly control a fluorescent bulb. A dedicated timing section in the L6574 allows the user set the necessary parameters for proper preheat and ignition of the lamp. Also, an OP AMP is available to implement closed loop control of the lamp current during normal lamp burning. An integrated bootstrap section, eliminating the normally required bootstrap diode and the zener clamping on Vs, makes the L6574 well suited for low cost applications where few additional components are needed to build a high performance ballast.
DESCRIPTION In order to ensure voltage ratings in excess of 600V, the L6574 is manufactured with BCD OFF LINE technology, which makes it well suited for lamp ballast applications. BLOCK DIAGRAM
H.V. VS OP AMP OPOUT OPINOPIN+ OUT Imin VREF DEAD TIME Ifs Imax VREF + RPRE CONTROL LOGIC Vthpre + VTHE EN2 VTHE EN1 Ipre DRIVING LOGIC LEVEL SHIFTER VS LVG RING LVG DRIVER GND VBOOT
+ UV DETECTION BOOTSTRAP DRIVER HVG DRIVER
HVG
CBOOT LOAD
+ -
+ -
VCO Cf
CPRE
D97IN493A
September 2003
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L6574
PIN CONNECTION (top view)
CPRE RPRE CF RING OPOUT OPINOPIN+ EN1
1 2 3 4 5 6 7 8
D97IN492
16 15 14 13 12 11 10 9
VBOOT HVG OUT N.C. VS LVG GND EN2
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction to ambient Max. DIP16 80 SO16N 120 Unit °C/W
PIN DESCRIPTION
N° 1 Pin CPRE Function Preheat Timing Capacitor. The capacitor CPRE sets the preheating and the frequency shift time, according to the relations: tPRE = KPRE · CPRE and tSH = KFS · CPRE (typ. KPRE = 1.5s/µF, KFS = 0.15s/µF). This feature is obtained by charging CPRE with two different currents. During tPRE this current is independent of the external components, so CPRE is charged up to 3.5V (preheat timing comparator threshold). During tSH the current depends on RPRE value (i.e. on the difference between fPRE and fIGN). In this way tSH is always set at 0.1tPRE. In steady state the voltage at pin 1 is 5V. Maximum Oscillation Frequency Setting. The resistance connected between this pin and ground sets the fPRE value, fixing the difference between fPRE and fIGN (fPRE > fIGN). At the end of the Start-up procedure, the effect current drown from RPRE is over. The voltage at this pin is fixed at VREF =2V. Oscillator Frequency Setting. The capacitor CF, along with to RPRE and RIGN, sets fPRE and fING. In normal operation this pin shows a triangular wave. Minimum Oscillation Frequency Setting. The resistance connected between this pin and ground sets the fIGN value. The voltage at this pin is fixed at VREF =2V. Out of the operational amplifier. To implement a feedback control loop this pin can be connected to the RIGN pin by means an appropriate circuitry. Inverting Input of the operational amplifier. Non Inverting Input of the operational amplifier. Enable 1. This pin (active high), forces the device in a latched shutdown state (like in the under voltage conditions). There are two ways to resume normal operation: the first is to reduce the supply voltage below the undervoltage threshold and then increase it again until the valid supply is recognised. the second is activating EN2 input. The enable 1 is especially designed for strong fault (e.g. in case of lamp disconnection).
2
RPRE
3 4 5 6 7 8
CF RIGN OPout OPinOPin+ EN1
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L 6574
PIN DESCRIPTION (continued)
N° 9 10 11 Pin EN2 GND LVG Function Enable 2. EN2 input (active high) restarts the start-up procedure (preheating and ignition sequence). This features is useful if the lamp does not turn-on after the first ignition sequence . Ground. Low Side Driver Output. This pin must be connected to the low side power MOSFET gate of the half bridge. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. Supply Voltage. This pin, connected to the supply filter capacitor, is internally clamped (15.6V typical). Non Connected. This pin set a distance between the pins related to the HV and those related to the LV side. High Side Driver Floating Reference. This pin must be connected close to the source of the high side power MOS or IGBT. High Side Driver Output. This pin must be connected to the high side power MOSFET gate of the half bridge. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. Bootstrapped Supply Voltage. Between this pin and VS must be connected the bootstrap capacitor. A patented integrated circuitry replaces the external bootstrap diode, by means of a high voltage DMOS, synchronously driven with the low side power MOSFET.
12 13 14 15
VS N.C. OUT HVG
16
VBOOT
ABSOLUTE MAXIMUM RATINGS
Symbol IS VLVG VOUT VHVG VBOOT dVBOOT/dt dVOUT/dt Vir Vic VEN1, VEN2 IEN1, IEN2 Vopc Vopd Vopo Tstg, Tj Tamb Supply Current (*) Low Side Output High Side Reference High Side Output Floating Supply Voltage VBOOT pin Slew rate (repetitive) OUT pin Slew Rate (repetitive) Forced Input Voltage (pins Ring, Rpre) Forced Input Voltage (pins Cpre, Cf) Enable Input Voltage Enable Input Current Sense Op Amp Common Mode Range Sense Op Amp Differential Mode Range Sense Op Amp Output Voltage (forced) Storage Temperature Ambient Temperature Parameter Value 25 -0.3 to Vs +0.3 -1 to VBOOT -18 -1 to VBOOT -1 to 618 ±50 ±50 -0.3 to 5 -0.3 to 5 -0.3 to 5 ±3 -0.3 to 5 ±5 4.6 -40 to +150 -40 to +125 Unit mA V V V V V/ns V/ns V V V mA V V V °C °C
(*) The device has an internal Clamping Zener between GND and the VCC pin, it must not be supplied by a Low Impedance Voltage Source. Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to 900V (Human Body Model)
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