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Part: M24C32-S
Category:
Memory
-> ROM
-> EEPROM
-> 32 Kb
Description: 32Kb (x8), 1.8-3.6V, 400kHz, 10ms Write Time
Company: ST Microelectronics, Inc.
Datasheet: Download M24C32-S datasheet File size : 13 kB
Request For quote: Find where to buy M24C32-S
Datasheet text preview:
M24C64 M24C32
64Kbit and 32Kbit Serial I²C Bus EEPROM
FEATUR ES SUMMARY 2 s Two Wire I C Serial Interface Supports 400 kHz Protocol
s
Figure 1. Packages
Single Supply Voltage: 4.5V to 5.5V for M24Cxx 2.5V to 5.5V for M24Cxx-W 1.8V to 5.5V for M24Cxx-R
s s s s s s s s
Write Control Input BYTE and PAGE WRITE (up to 32 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
8 1
PDIP8 (BN)
8 1
SO8 (MN) 150 mil width
TSSOP8 (DW) 169 mil width
TSSOP8 (DS) 3x3mm² body size (MSOP)
February 2003
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M24C64, M24C32
SUMMARY DESCRIPTION These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8192 x 8 bits (M24C64) and 4096 x 8 bits (M24C32). Figure 2. Logic Diagram
VCC
Table 1. Signal Names
E0, E1, E2 SDA SCL WC VCC Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground
3 E0-E2 SCL WC M24C64 M24C32 SDA
VSS
VSS
AI01844B
Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR threshold value, and all operations are disabled the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal.
These devices are compatible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 3. DIP, SO and TSSOP Connections
M24C64 M24C32 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI01845C
VCC WC SCL SDA
Note: 1. See page 18 (onwards) for package dimensions, and how to identify pin-1.
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M24C64, M24C32
SIGNA L DESCRIPTION Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to V CC. (Figure 4 indicates how the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to V CC or VSS, to establish the Device Select Code. Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.
Figure 4. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
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Others parts begin by m2
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