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Part: M27C160-150XM1TR
Category:
Memory
-> EPROM
-> 8 Mb
Description: 16 Mbit 2mb x8 or 1mb X16 uv EPROM And OTP EPROM
Company: ST Microelectronics, Inc.
Datasheet: Download M27C160-150XM1TR datasheet File size : 45 kB
Request For quote: Find where to buy M27C160-150XM1TR
Datasheet text preview:
M27C160
16 Mbit (2Mb x8 or 1Mb x16) UV EPROM and OTP EP ROM
s
5V ± 10% SUPPLY VOLTAGE in READ OPERATION FAST ACCESS TIME: 70ns BYTE-WIDE or WORD-WIDE CONFIGURA BLE 16 M bit M ASK ROM REPLACEMENT
1 1 42 42
s s
s s
LOW PO WER CONSUMPTION Active Current 70mA at 8MHz Standby Current 100µA
FDIP 42W (F) P DIP42 (B)
s s s
PROG RAMMING VOLTAGE: 12.5V ± 0.25V PROG RAMMING TIME: 100µs/byte (typical) ELECTRONIC SIGNATURE M anufacturer Code: 0020h Device Code: 00B1h
PLCC44 (K )
1 44
SO44 (M)
DESCRIPTION The M 27C160 is a 16 Mbit EPROM offered i n the two ranges UV (ultra violet erase) and O TP (one time programmable). It is i deally suited for microprocessor systems requiring large data or program storage and is organised as either 2 Mbit words of 8 bit or 1 Mbit words of 16 bit. The pin-out is compatible with a 16 Mbit Mask ROM. The FDIP42W (window ceramic fri t-seal package) has a t ransparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. Table 1. Signal Names
A 0-A19 Q 0-Q7 Q 8-Q14 Q 15A1 E G B YTEVPP VCC VSS February 1999 Address Inputs Data Outp uts Data Outp uts Data Outp ut / A ddress Inp ut Chip Enable Output Enable Byte Mode / Pr ogram Su pply Supply Voltage Ground
Figure 1. Logic Diagram
VCC
20 A0-A19 15
Q15A1
Q0-Q14 E G BYTEVPP M27C160
VSS
AI00739B
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M27C160
Figure 2A. DIP Pin Connections
A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 2 3 4 5 6 7 8 9 10 M27C160 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
Figure 2B. PLCC Pin Connections
A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1
A5 A6 A7 A17 A18 VSS A19 A8 A9 A10 A11 1 44 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A1 Q7 Q14 Q6 12 M27C160 34 23 Q9 Q2 Q10 Q3 Q11 NC VCC Q4 Q12 Q5 Q13
AI03012
AI00740
Warning: NC = Not Connected.
Figure 2C. SO Pin Co nnections
NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11
1 2 3 4 5 6 7 8 9 10 11 M27C160 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
A new pattern can then be written rapidly to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C160 is offered in PDIP42, PLCC44 and SO44 packages. DEVICE OPERATION The operating modes of the M27C160 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatible except for VPP and 12V on A9 for the Electronic Signature. Read M ode The M 27C160 has two organisations, Word-wide and Byte-wide. The organisation is selected by the signal level on the BYTEVPP pin. When BYTEVPP is at VIH the Word-wide organisation is selected and t he Q15A1 pin is used for Q15 Data O utput. When the BYTEVPP pin i s at VIL the Byte-wide organisation is selected and the Q15A1 pin is used for the Address I nput A1. When the memory is logically regarded as 16 bit wide, but read i n the Byte-wide organisation, then with A1 at VIL t he lower 8 bits of the 16 bit data are selected and with A1 at VIH the upper 8 bits of the 16 bit data are selected.
AI01264
2/16
M2 7C 160
Table 2. Absolute Maximum Ratings (1)
Symbol TA TB IAS TSTG VIO (2) VCC VA9 (2) VP P Parameter Am bient Operat ing Temperature (3) Temperature Under Bias Sto rage Temperature Inp ut or Outp ut Voltage (except A9 ) Su pply Voltage A9 Voltage Pro gram Supply Voltage Value 40 to 125 50 to 125 65 to 150 2 to 7 2 to 7 2 to 13.5 2 to 14 Unit °C °C °C V V V V
Note: 1. Except for the rating " Operating T emperature R ange", stresses above those liste d in the Table "A bsolute Maximum R atings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above t hose indicated in t he Operating sections of t his s pecification is not impl ied. Exposure t o A bsolute M aximum R ating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or O utput is 0.5V with possible undershoot to 2.0V for a period les s than 20ns. M aximum DC voltage on O utput is VCC +0.5V with possible overshoot to VCC + 2V for a period less than 20ns. 3. Depends on range.
Table 3. Oper ating Modes
Mode R ead Word-wide R ead Byte-w ide U pper R ead Byte-w ide L ower O utput Disable P rogram Verify P rogram In hibit S tandby E lectronic Si gnature E VIL VIL VIL VIL VIL Pulse VIH VIH VIH VIL G VIL VIL VIL V IH V IH VIL V IH X VIL B YTEVPP V IH VIL VIL X V PP V PP V PP X V IH A9 X X X X X X X X V ID Q0-Q 7 D ata O ut D ata O ut D ata O ut Hi-Z Data In D ata O ut Hi-Z Hi-Z Codes Q 8-Q14 Data O ut Hi-Z Hi-Z Hi-Z D ata I n Data O ut Hi-Z Hi-Z Codes Q15A1 D ata Out VIH V IL Hi-Z Data I n D ata Out Hi-Z Hi-Z Code
Note: X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic Signature
Ide ntifie r M anufacturer's Code D evice Code A0 VIL VIH Q7 0 1 Q6 0 0 Q5 1 1 Q4 0 1 Q3 0 0 Q2 0 0 Q1 0 0 Q0 0 1 Hex Data 20h B1h
Note: Outputs Q8-Q15 are set to '0'.
The M 27C160 has t wo control f unctions, both of which must be logically active in order to obtain data at the outputs. In addition t he Word-wide or Byte- wide organisation must be s elected. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and s hould be used t o gate data to
the output pins independent of device selection. Assuming t hat the addresses are st able, the address access t ime (tAVQV) i s equal to the delay from E to output (tE LQV). Data is available at t he output after a delay of tGLQV from th e falling edge of G, assuming that E has been low and th e addresses have been stable for at least tAV QV-tGLQV.
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