Details, datasheet, quote on part number: M27C2001-10F1
PartM27C2001-10F1
Category
Description2 Megabit -256k X 8- uv EPROM And OTP ROM
CompanyST Microelectronics, Inc.
DatasheetDownload M27C2001-10F1 datasheet
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Features, Applications

VERY FAST ACCESS TIME: 70ns COMPATIBLE with HIGH SPEED MICROPROCESSORS, ZERO WAIT STATE LOW POWER "CMOS" CONSUMPTION: Active Current 30mA Standby Current 100A PROGRAMMING VOLTAGE: 12.75V ELECTRONIC SIGNATURE for AUTOMATED PROGRAMMING TIMES of AROUND 24sec. (PRESTO II ALGORITHM)

DESCRIPTION The is a high speed 2 Megabit UV erasable and programmable memory (EPROM) ideally suited for microprocessor systems requiring large programs. It isorganised by 8 bits. The 32 pin Window Ceramic Frit-Seal Dual-in-Line and Leadless Chip Carrier packages have transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C2001 is offered in both Plastic Leaded Chip Carrier and Plastic Thin Small Outline packages.

G P VPP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Program Supply Voltage Ground

DEVICE OPERATION The modes of operations of the M27C2001 are listed in the Operating Modes table. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vpp and on A9 for Electronic Signature. Read Mode The M27C2001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C2001 has a standby mode which reduces the active current from to 100A. The M27C2001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.

Parameter Ambient Operating Temperature Under Bias Storage Temperature Input or Output Voltages (except A9) Supply Voltage A9 Voltage Program Supply Voltage

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature
- Q7 Data Out Hi-Z Data In Data Out Hi-Z Codes
Identifier Manufacturer's Code Device Code A0 VIL VIH 0 1 Hex Data 20h 61h

Two Line Output Control BecauseEPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur.

For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.


 

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