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Part: M27V160-150XB6TR
Category:
Memory
-> EPROM
-> 8 Mb
Description: 16 Mbit 2mb x8 or 1mb X16 Low Voltage uv EPROM And OTP EPROM
Company: ST Microelectronics, Inc.
Datasheet: Download M27V160-150XB6TR datasheet File size : 45 kB
Request For quote: Find where to buy M27V160-150XB6TR
Datasheet text preview:
M27V160
16 Mbit (2Mb x8 or 1Mb x16) Low Voltage UV EPROM and OTP EP ROM
s
3V to 3.6V LOW VOLTAGE in READ OPERATION ACCESS TIME: 100ns BYTE-WIDE or WORD-WIDE CONFIGURA BLE 16 M bit M ASK ROM REPLACEMENT LOW PO WER CONSUMPTION Active Current 30mA at 8MHz Standby Current 60µA
1 1 42 44
s s
s s
F DIP42W (F)
SO44 (M)
s s s
PROG RAMMING VOLTAGE: 12.5V ± 0.25V PROG RAMMING TIME: 50µs/word ELECTRONIC SIGNATURE
42
M anufacturer Code: 20h Device Code: B1h DESCRIPTION The M27V160 is a low voltage 16 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program st orage. I t is organised as either 2 Mbit words of 8 bit or 1 Mbit words of 16 bit. The pin-out is compatible with a 16 Mbit Mask ROM. The M 27V160 operates in t he read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. The FDIP42W (window ceramic fri t-seal package) has a t ransparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written rapidly to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27V160 is offered in PDIP42 and SO44 packages.
1
PDIP 42 (B )
Figure 1. Logic Diagram
VCC
20 A0-A19 15
Q15A1
Q0-Q14 E G BYTEVPP M27V160
VSS
AI01898
Marc h 2000
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M27V160
Figure 2A. DIP Connections Figure 2B. SO Connections
A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11
1 2 3 4 5 6 7 8 9 10 M27V160 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
AI01899
NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11
1 2 3 4 5 6 7 8 9 10 11 M27V160 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
AI01900
Table 1. Signal Names
A 0-A19 Q 0-Q7 Q 8-Q14 Q 15A1 E G B YTEVPP VCC VSS NC Address Inputs Data Outp uts Data Outp uts Data Outp ut / A ddress Inp ut Chip Enable Output Enable Byte Mode / Pr ogram Su pply Supply Voltage Ground Not Connected Inter nally
DEVICE OPERATION The operating modes of the M27V160 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatible except for VPP and 12V on A9 for the Electronic Signature. Read M ode The M 27V160 has two organisations, Word-wide and Byte-wide. The organisation is selected by the signal level on the BYTEVPP pin. When BYTEVPP is at VIH the Word-wide organisation is selected and t he Q15A1 pin is used for Q15 Data O utput. When the BYTEVPP pin i s at VIL the Byte-wide organisation is selected and the Q15A1 pin is used for the Address I nput A1. When the memory is logically regarded as 16 bit wide, but read i n the Byte-wide organisation, then with A1 at VIL t he lower 8 bits of the 16 bit data are selected and with A1 at VIH the upper 8 bits of the 16 bit data are selected.
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M 27V160
Table 2. Absolute Maximum Ratings (1)
Symbol TA TB IAS TSTG VIO (2) VCC VA9 (2) VP P Parameter Am bient Operat ing Temperature (3) Temperature Under Bias Sto rage Temperature Inp ut or Outp ut Voltage (except A9 ) Su pply Voltage A9 Voltage Pro gram Supply Voltage Value 40 to 125 50 to 125 65 to 150 2 to 7 2 to 7 2 to 13.5 2 to 14 Unit °C °C °C V V V V
Note: 1. Except for the rating " Operating T emperature R ange", stresses above those liste d in the Table "A bsolute Maximum R atings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above t hose indicated in t he Operating sections of t his s pecification is not impl ied. Exposure t o A bsolute M aximum R ating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or O utput is 0.5V with possible undershoot to 2.0V for a period les s than 20ns. M aximum DC voltage on O utput is VCC +0.5V with possible overshoot to VCC + 2V for a period less than 20ns. 3. Depends on range.
Table 3. Oper ating Modes
Mode R ead Word-wide R ead Byte-w ide U pper R ead Byte-w ide L ower O utput Disable P rogram Verify P rogram In hibit S tandby E lectronic Si gnature E VIL VIL VIL VIL VIL Pulse VIH VIH VIH VIL G VIL VIL VIL V IH V IH VIL V IH X VIL B YTEVPP V IH VIL VIL X V PP V PP V PP X V IH A9 X X X X X X X X V ID Q 15A1 D ata O ut VIH VIL Hi-Z Data In D ata O ut Hi-Z Hi-Z Code Q 14-Q8 Data O ut Hi-Z Hi-Z Hi-Z D ata I n Data O ut Hi-Z Hi-Z Codes Q7 -Q0 D ata Out D ata Out D ata Out Hi-Z Data I n D ata Out Hi-Z Hi-Z Codes
Note: X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic Signature
Ide ntifie r M anufacturer's Code D evice Code A0 VIL VIH Q 15 and Q7 0 1 Q 14 a nd Q6 0 0 Q13 and Q5 1 1 Q 12 and Q4 0 1 Q11 and Q3 0 0 Q10 and Q2 0 0 Q9 and Q1 0 0 Q8 and Q0 0 1 Hex Data 20h B1h
The M27V160 has two c ontrol functions, both of which must be logically active in order to obtain data at the outputs. In addition t he Word-wide or Byte- wide organisation must be s elected. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and s hould be used t o gate data to
the output pins independent of device selection. Assuming t hat the addresses are st able, the address access t ime (tAVQV) i s equal to the delay from E to output (tE LQV). Data is available at t he output after a delay of tGLQV from th e falling edge of G, assuming that E has been low and th e addresses have been stable for at least tAV QV-tGLQV.
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