Details, datasheet, quote on part number: M28C17-120K1T
CategoryDiscrete => Diodes & Rectifiers => Protection
Description16k 2k X 8 Parallel EePROM With Software Data Protection
CompanyST Microelectronics, Inc.
DatasheetDownload M28C17-120K1T datasheet


Features, Applications

FAST ACCESS TIME: 90ns SINGLE 10% SUPPLY VOLTAGE LOW POWER CONSUMPTION FAST WRITE CYCLE: 64 Bytes Page Write Operation Byte or Page Write Cycle: 3ms Max ENHANCED END OF WRITE DETECTION: Ready/Busy Open Drain Output Data Polling Toggle Bit PAGE LOAD TIMER STATUS BIT HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY: Endurance >100,000 Erase/Write Cycles Data Retention >40 Years JEDEC APPROVED BYTEWIDE PIN OUT SOFTWARE DATA PROTECTION M28C17 is replaced by the products described on the document M28C16A DESCRIPTION The x 8 low power Parallel EEPROM fabricated with SGS-THOMSON proprietary single polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 5V power supply. The M28C17 offers the same features than the M28C16, in addition to the Ready/Busy pin. The circuit has been designed to offer a flexible microcontroller interface featuring both hardware Table 1. Signal Names

G RB VCC VSS Address Input Data Input / Output Write Enable Chip Enable Output Enable Ready / Busy Supply Voltage Ground

This is information on a product still in production but not recommended for new design.

DESCRIPTION (cont'd) and software handshaking with Ready/Busy, Data Polling and Toggle Bit. The M28C17 supports 64 byte page write operation. A Software Data Protection (SDP) is also possible using the standard JEDEC algorithm. PIN DESCRIPTION Addresses (A0-A10). The address inputs select an 8-bit memory location during a read or write operation. Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/ Out - DQ7). Data is written to or read from the M28C17 through the I/O pins. Write Enable (W). The Write Enable input controls the writing of data to the M28C17. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle.

Symbol TA TSTG VCC VIO VI VESD Parameter Ambient Operating Temperature Storage Temperature Range Supply Voltage Input/Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. 100pF through MIL-STD-883C, 3015.7

Mode Standby Output Disable Write Disable Read Write - DQ7 Hi-Z Data Out Data In

OPERATION In order to prevent data corruption and inadvertent write operations an internal VCC comparator inhibits Write operation if VCC is below VWI (see Table 7). Access to the memory in write mode is allowed after a power-up as specified in Table 7. Read The M28C17 is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedance when either E is high. Write operations are initiated when both W and E are low and G is high.The M28C17 supports both E and W controlled write cycles. The Address is latched by the falling edge or W which ever occurs last and the Data on the rising edge or W which ever occurs first. Once initiated the write operation is internally timed until completion.

Page Write Page write allows to 64 bytes to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A6-A10 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data with a minimum data transfer rate of 1/tWHWH (see Figure If a transition W is not detected within tWHWH, the internal programming cycle will start. Chip Erase The contents of the entire memory may be erased to FFh by use of the Chip Erase command by setting Chip Enable (E) Low and Output Enable (G) to VCC + 7.0V. The chip is cleared when a 10ms low pulse is applied to the Write Enable pin.


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