Details, datasheet, quote on part number: M28C64C-250MS1
PartM28C64C-250MS1
CategoryMemory => ROM => EEPROM
Description64 Kbit 8kb x8 Parallel EePROM
CompanyST Microelectronics, Inc.
DatasheetDownload M28C64C-250MS1 datasheet
  

 

Features, Applications

FAST ACCESS TIME: 150ns SINGLE 10% SUPPLY VOLTAGE LOW POWER CONSUMPTION FAST WRITE CYCLE 32 Bytes Page Write Operation Byte or Page Write Cycle: 5ms ENHANCED END OF WRITE DETECTION Ready/Busy Open Drain Output (for M28C64C product only) Data Polling Toggle Bit PAGE LOAD TIMER STATUS BIT HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY Endurance >100,000 Erase/Write Cycles Data Retention >40 Years JEDEC APPROVED BYTEWIDE PIN OUT DESCRIPTION The an 8 Kbit x8 low power Parallel EEPROM fabricated with STMicroelectronics proprietary single polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 5V power supply. The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshakingmode with Ready/Busy, Data Polling and Toggle Bit. The M28C64C supports 32 byte page write operation. Table 1. Signal Names

G RB VCC VSS Address Input Data Input / Output Write Enable Chip Enable Output Enable Ready / Busy Supply Voltage Ground


PIN DESCRITPION Addresses (A0-A12). The address inputs select an 8-bit memory location during a read or write operation.

Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations.

Symbol TA T STG VCC IO VI VESD Parameter Ambient Operating Temperature Storage Temperature Range Supply Voltage Input/Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model) Value 0.3 to VCC 6.5 2000 Unit C

Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

Mode Read Write Standby / Write Inhibit Write Inhibit Write Inhibit Output Disable
- DQ7 Data Out Data In Hi-Z Data Out or Hi-Z Data Out or Hi-Z

Data In/ Out - DQ7). Data is written to or read from the M28C64C through the I/O pins. Write Enable (W). The Write Enable input controls the writing of data to the M28C64C. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. OPERATION In order to prevent data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit resets all internal programming cicuitry. Access to the memory in write mode is allowed after a power-up as specified in Table 6. Read The M28C64C is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedancewhen either E is high.

Write operations are initiated when both W and E are low and G is high.The M28C64C supports both E and W controlled write cycles. The Address is latched by the falling edge or W which ever occurs last and the Data on the rising edge or W which ever occurs first. Once initiated the write operation is internally timed until completion. Page Write Page write allows to 32 bytes to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that - A12 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data to a maximum of 100s after the rising edge or W which ever occurs first (t BLC). If a transition W is not detected within 100s, the internal programming cycle will start.


 

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