|Category||Memory => Flash => NOR Flash => Advanced Architecture Boot Block 1.8V|
|Title||Advanced Architecture Boot Block 1.8V|
|Description||Known Good Die 4 Mbit (256KB X16) 1.8V Supply Flash Memory|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download M28R400CB datasheet
|Known Good Die 4 Mbit (256Kb x16, Boot Block) 1.8V Supply Flash Memory
FEATURES SUMMARY s SUPPLY VOLTAGE VDD to 2.2V Core Power Supply VDDQ= to 2.2V for Input/Output VPP = 12V for fast Program (optional)ACCESS TIME: 100ns PROGRAMMING TIME 10µs typical Double Word Programming Option
COMMON FLASH INTERFACE 64 bit Security Code MEMORY BLOCKS Parameter Blocks (Top or Bottom location) Main Blocks
BLOCK LOCKING All blocks locked at Power Up Any combination of blocks can be locked WP for Block Lock-Down
SECURITY 64 bit user Programmable OTP cells 64 bit unique device identifier One Parameter Block Permanently Lockable
AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, 882Ah Bottom Device Code, M28R400CB: 882Bh
TABLE OF CONTENTS SUMMARY DESCRIPTION. 5 Figure 2. Logic Diagram. 3 Table 1. Signal Names. 3 FUNCTIONAL SPECIFICATION. 4 Table 2. Product Specification. 4 Table 3. Operating Conditions. 4 Table 4. Read AC Characteristics. 4 Table 5. Write AC Characteristics. 4 Table 6. Physical Specification. 4 Table 7. Manufacturing Information. 4 DIE SPECIFICATIONS. 5 Figure 3. Die Photograph and Pad Location. 5 Figure 4. Wafer/Die Orientation. 5 Table 8. Pad Extraction. 6 PRODUCT TEST FLOW. 7 Figure 5. Product Test Flow. 7 HANDLING INSTRUCTIONS Processing. 8 Storage. 8 PART NUMBERING. 9 Table 9. Ordering Information Scheme. 9 REVISION HISTORY. 10 Table 10. Document Revision History. 10
SUMMARY DESCRIPTION The M28R400C are available as Known Good Dice. STMicroelectronics defines Known Good Dice as standard products offered as dice and tested for functionality and speed. ST's Known Good Die products are as reliable and of the same quality as products delivered in packages. This datasheet should be read in conjunction with the full M28R400C datasheet. The a 4 Mbit x 16) non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage to 2.2V) supply. VDDQ allows to drive the I/O pin down 1.65V. An optional 12V VPP power supply is provided to speed up customer programming. The device features an asymmetrical blocked architecture. The M28R400C has an array of 15 blocks: 8 Parameter Blocks of 4 KWord and 7 Main Blocks of 32 KWord. M28R400CT has the Parameter Blocks at the top of the memory address space while the M28R400CB locates the Parameter Blocks starting from the bottom. The M28R400C features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and block erase. When VPP £ VPPLK all blocks are protected against program or block erase. All blocks are locked at power-up. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The device includes a 128 bit Protection Register and a Security Block to increase the protection of a system design. The Protection Register is divided into two 64 bit segments, the first one contains a unique device number written by ST, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The M28R400C are supplied with all the bits erased (set to `1') Figure 2. Logic Diagram
RP WP VDD VDDQ VPP VSS Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Reset Write Protect Core Power Supply Power Supply for Input/Output Optional Supply Voltage for Fast Program & Erase Ground
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