|Category||Memory => Flash|
|Description||16 Mbit 1mb X16, Boot Block Low Voltage Flash Memory|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download M28W160BTB100GB1T datasheet
|16 Mbit (1Mb x16, Boot Block) Low Voltage Flash Memory
SUPPLY VOLTAGE VDD to 3.6V: for Program, Erase and Read VDDQ or 2.7V: Input/Output option VPP = 12V: optional Supply Voltage for fast ProgramPROGRAMMING TIME: 10µs typical Double Word Programming Option
PROGRAM/ERASE CONTROLLER (P/E.C.) COMMON FLASH INTERFACE 64 bit Security Code MEMORY BLOCKS Parameter Blocks (Top or Bottom location) Main Blocks Figure 1. Logic DiagramBLOCK PROTECTION on TWO PARAMETER BLOCKS WP for Block Protection
AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS of DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, 90h Bottom Device Code, M28W160BB: 91hFigure 2. µBGA Connections (Top view through package)
RP WP VDD VDDQ VPP VSS NC Address Inputs Data Input/Output, Command Inputs Data Input/Output Chip Enable Output Enable Write Enable Reset Write Protect Supply Voltage Power Supply for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Not Connected Internally
Symbol TA TBIAS TSTG VIO VDD, VDDQ VPP Parameter Ambient Operating Temperature (2) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Value to 13 Unit °C V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range.
DESCRIPTION The a 16 Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-byWord basis. The device is offered in the x 20mm) and the µBGA46, 0.75mm ball pitch packages. When shipped, all bits of the M28W160B are in the `1' state. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Each block can be programmed and erased over 100,000 cycles. V DDQ allows to drive the I/O pin down 1.65V. An optional 12V VPP power supply is provided to speed up the program phase at customer production line environment. An internal Command Interface (C.I.) decodes the instructions to access/modify the memory content. The Program/Erase Controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Verification is performed too, unburdening the microcontroller, while the Status Register tracks the status of the operation. The following instructions are executed by the M28W160B: Read Array, Read Electronic Signature, Read Status Register, Clear Status Register, Program, Double Word Program, Block Erase, Program/Erase Suspend, Program/Erase Resume and CFI Query.
Organisation The M28W160B is organised as 1 Mbit by 16 bits. A0-A19 are the address lines; DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. The upper two (or lower two) parameter blocks can be protected to secure the code content of the memory. WP controls protection and unprotection operations. Memory Blocks The device features an asymmetrical blocked architecture. The M28W160B has an array of 39 blocks: 8 Parameter Blocks of 4 KWord and 31 Main Blocks of 32 KWord. M28W160BT has the Parameter Blocks at the top of the memory address space while the M28W160BB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Tables 3 and 4. The two upper parameter block can be protected from accidental programming or erasure using WP. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed.
|Related products with the same datasheet|
|Some Part number from the same manufacture ST Microelectronics, Inc.|
|M28W160BTB100GB6T 16 Mbit 1mb X16, Boot Block Low Voltage Flash Memory|
|M28W160CB 16 Mbit (1MB X16, Boot BLOCK) 3V Supply Flash Memory|
|M28W160ECB 16 Mbit (1Mbx16, Boot Block) 3V Supply Flash Memory|
|M28W320BB 32 Mbit (2MB X16, Boot BLOCK) 3V Supply Flash Memory|
|M28W320C-GBT 32 Mbit 2mb X16, Boot Block Low Voltage Flash Memory|
|M28W320CB 32 Mbit (2MB X16, Boot BLOCK) 3V Supply Flash Memory|
|M28W320CB100GB1T 32 Mbit 2mb X16, Boot Block Low Voltage Flash Memory|
|M28W320CB70N6 32 Mbit (2MB X16, Boot BLOCK) 3V Supply Flash Memory|
|M28W320CB90GB1T 32 Mbit 2mb X16, Boot Block Low Voltage Flash Memory|
|M28W320CB90N6 32 Mbit (2MB X16, Boot BLOCK) 3V Supply Flash Memory|
|M28W320CB90N6T 32 Mbit 2mb X16, Boot Block Low Voltage Flash Memory|
|M28W320CT 32 Mbit (2MB X16, Boot BLOCK) 3V Supply Flash Memory|
|M28W320CT100GB1T 32 Mbit 2mb X16, Boot Block Low Voltage Flash Memory|
|M28W320CT70N6 32 Mbit (2MB X16, Boot BLOCK) 3V Supply Flash Memory|
|M28W320CT90GB1T 32 Mbit 2mb X16, Boot Block Low Voltage Flash Memory|
|M28W320CT90N1 32 Mbit (2MB X16, Boot BLOCK) 3V Supply Flash Memory|
|M28W320CT90N1T 32 Mbit 2mb X16, Boot Block Low Voltage Flash Memory|
|M28W320CT90N6 32 Mbit (2MB X16, Boot BLOCK) 3V Supply Flash Memory|
72V3656 : 2K X 36 X 2 Triple-bus Fifo, 3.3V. 3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING x 2 Memory storage capacity: x 2 Clock frequencies to 100 MHz (6.5ns access time) Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives and Port B transmits) 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports.
Am29PDL640AGa85N : 64Mbit (4M X16-Bit) CMOS 3.0 Volt-Only, Simultaneous Operation Flash Memory And 16Mbit (1M X16-Bit) Pseudo Static RAM.
DPS1MX8MY5 : SRAM, 8 Megabits. 8 Megabit CMOS SRAM 16 Megabit CMOS SRAM : The LP-StackTM series is a family of interchangeable memory modules. The 4 Megabit SRAM is a member of this family which utilizes the new and innovative space saving TSOP technology. The modules are constructed with 8, 5 Volt SRAM's. The 4 Megabit based LP-StackTM modules have been designed to fit in the same.
DSM2150F5V : DSP System Memories. DSM (DIGITAL Signal Processor System MEMORY) For Analog Devices DSPS (3.3V SUPPLY).
IC41C1665 : . The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the s and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. The ICSI IC41C1665 and the IC41LV1665 are x 16Fast access and cycle time bit high-performance CMOS Dynamic Random Access.
IDT70V9389 : 64K X 18 Synch, 3.3V Dual-port RAM, Pipelined/flow-through. True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 6/7.5/9/12ns (max.) Industrial: 9ns (max.) Low-power operation IDT70V9389/289L Active: 500mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable.
IS61C64AH : . High-speed access time: 20, 25 ns Automatic power-down when chip is deselected CMOS low power operation 450 mW (typical) operating 250 µW (typical) standby TTL compatible interface levels Single 5V power supply Fully static operation: no clock or refresh required Three state outputs Two Chip Enables (CE1 and CE2) for simple memory expansion The ICSI.
K9F2808U0A : 16m X 8 Bit NAND Flash Memory. 0.1 0.2 Initial issue. 1. Revised real-time map-out algorithm(refer to technical notes) 1. Changed device name K9F2808U0A-YIB0 1. Changed sequential row read opera tion - The Sequential Read 1 and 2 operation is allowed only within a block 2. Changed invalid block(s) marking method prior to shipping - The invalid block(s) information is written the or 2nd page.
MBM30LV0128 : 128 M ( 16 M X 8 ) Bit NAND-type. The MBM30LV0128 device is a single × 8 bit NAND flash memory organized as 528 byte × 32 pages × 1024 blocks. Each 528 byte page contains 16 bytes of optionally selected spare area which may be used to store ECC code ( s indicated are on condition that ECC system would be combined). Program and read data is transferred between the memory array and page.
MCM63P733A : 128k X 32 Bit Pipelined Burstram Synchronous Fast Static RAM. The a 4Mbit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPCTM and other high performance microprocessors. It is organized as 128K words of 32 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2bit address.
MH16V644AWJ : FPM. Fast Page Mode 1g (16mx64) DRAM. FAST PAGE MODE 1073741824 - BIT 16777216 - WORD 64 - BIT ) DYNAMIC RAM PIN CONFIGURATION The x 64-bit dynamic ram module. This consist of sixteen industry standard x 4 dynamic RAMs in SOJ and one industry standard EEPROM in TSSOP. The mounting of SOJs and TSSOP on a card edge dual in-line package provides any application where high densities and large.
MS81V04160A : DRAMs and ASMs->Field DRAM. Dual Fifo 256K X 8 X 2. The is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO (First-In First-Out) memories which were designed for x 8-bit high-speed asynchronous read/write operation. The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in common. The MS81V04160, functionally compatible with Oki's 2Mb FIFO memory (MSM51V8222A),.
WS1M8 : MCPSRAM. Organization = 2x512Kx8 ;; Speed (ns) = 70-100 ;; Volt = 5 ;; Package = 32 Dip ;; Temp = C,i,m ;;.
CY7C161-12PC : 16K X 4 STANDARD SRAM, 12 ns, PDIP28. s: Memory Category: SRAM Chip ; Density: 66 kbits ; Number of Words: 16 k ; Bits per Word: 4 bits ; Package Type: DIP, DIP-28 ; Pins: 28 ; Logic Family: CMOS ; Supply Voltage: 5V ; Access Time: 12 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).
W3E16M72SR-250BC : 16M X 72 DDR DRAM, 0.75 ns, PBGA219. s: Memory Category: DRAM Chip ; Density: 1207960 kbits ; Number of Words: 16000 k ; Bits per Word: 72 bits ; Package Type: BGA, 32 X 25 MM, PLASTIC, BGA-219 ; Pins: 219 ; Supply Voltage: 2.5V ; Access Time: 0.7500 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).