|Category||Memory => Flash|
|Description||16 Mbit 1mb X16, Boot Block Low Voltage Flash Memory|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download M28W160BTB100GB1T datasheet
|16 Mbit (1Mb x16, Boot Block) Low Voltage Flash Memory
SUPPLY VOLTAGE VDD to 3.6V: for Program, Erase and Read VDDQ or 2.7V: Input/Output option VPP = 12V: optional Supply Voltage for fast ProgramPROGRAMMING TIME: 10µs typical Double Word Programming Option
PROGRAM/ERASE CONTROLLER (P/E.C.) COMMON FLASH INTERFACE 64 bit Security Code MEMORY BLOCKS Parameter Blocks (Top or Bottom location) Main Blocks Figure 1. Logic DiagramBLOCK PROTECTION on TWO PARAMETER BLOCKS WP for Block Protection
AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS of DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, 90h Bottom Device Code, M28W160BB: 91hFigure 2. µBGA Connections (Top view through package)
RP WP VDD VDDQ VPP VSS NC Address Inputs Data Input/Output, Command Inputs Data Input/Output Chip Enable Output Enable Write Enable Reset Write Protect Supply Voltage Power Supply for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Not Connected Internally
Symbol TA TBIAS TSTG VIO VDD, VDDQ VPP Parameter Ambient Operating Temperature (2) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Value to 13 Unit °C V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range.
DESCRIPTION The a 16 Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-byWord basis. The device is offered in the x 20mm) and the µBGA46, 0.75mm ball pitch packages. When shipped, all bits of the M28W160B are in the `1' state. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Each block can be programmed and erased over 100,000 cycles. V DDQ allows to drive the I/O pin down 1.65V. An optional 12V VPP power supply is provided to speed up the program phase at customer production line environment. An internal Command Interface (C.I.) decodes the instructions to access/modify the memory content. The Program/Erase Controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Verification is performed too, unburdening the microcontroller, while the Status Register tracks the status of the operation. The following instructions are executed by the M28W160B: Read Array, Read Electronic Signature, Read Status Register, Clear Status Register, Program, Double Word Program, Block Erase, Program/Erase Suspend, Program/Erase Resume and CFI Query.
Organisation The M28W160B is organised as 1 Mbit by 16 bits. A0-A19 are the address lines; DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. The upper two (or lower two) parameter blocks can be protected to secure the code content of the memory. WP controls protection and unprotection operations. Memory Blocks The device features an asymmetrical blocked architecture. The M28W160B has an array of 39 blocks: 8 Parameter Blocks of 4 KWord and 31 Main Blocks of 32 KWord. M28W160BT has the Parameter Blocks at the top of the memory address space while the M28W160BB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Tables 3 and 4. The two upper parameter block can be protected from accidental programming or erasure using WP. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed.
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