Details, datasheet, quote on part number: M295V100-T90XN1R
PartM295V100-T90XN1R
CategoryMemory => Flash
Description1 Mbit 128kb x8 or 64kb X16, Boot Block Single Supply Flash Memory
CompanyST Microelectronics, Inc.
DatasheetDownload M295V100-T90XN1R datasheet
  

 

Features, Applications
1 Mbit 64Kb x16, Boot Block) Single Supply Flash Memory

10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS FAST ACCESS TIME: 70ns FAST PROGRAMMING TIME 10s by Byte 16s by Word typical PROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte or Word-by-Word Status Register bits and Ready/Busy Output MEMORY BLOCKS Boot Block (Top or Bottom location) Parameter and Main blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTI-BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend LOW POWER CONSUMPTION Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code, 00D0h Device Code, M29F100B: 00D1h DESCRIPTION The is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byteor Wordby-Word basis using only a single 5V VCC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles.

A0-A15 Address Inputs Data Input/Outputs, Command Inputs Data Input/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset / Block Temporary Unprotect Ready/Busy Output Byte/Word Organisation Supply Voltage Ground

Parameter Ambient Operating Temperature Under Bias Storage Temperature Input or Output Voltages Supply Voltage

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns. 3. Depends on range.

DESCRIPTION (Cont'd) Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commandsto a Command Interfaceusing standard microprocessor write timings. The device is offered x 20mm) and SO44 packages. Both normal and reverse pinouts are available for the TSOP48 package. Organisation The M29F100 is organised 64Kb x16 bits selectable by the BYTE signal. When BYTE is Low the Byte-wide x8 organisation is selected and the address lines are DQ15A1 and A0-A15. The Data Input/Output signal DQ15A1 acts as address line A1 which selects the lower or upper Byte of the memory word for output DQ0-DQ7, DQ8-DQ14 remain at High impedance. When BYTE is High the memory uses the address inputs A0-A15 and the Data Input/Outputs DQ0DQ15. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. AReset/Block TemporaryUnprotection RP tri-level input provides a hardware reset when pulled Low, and when held High (at VID) temporarily unprotects blocks previously protected allowing them to be programed and erased. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of

the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms. Memory Blocks The devices feature asymmetrically blocked architecture providing system memory integration. Both M29F100T and M29F100B devices have an array of 5 blocks, one Boot Block of 16 KBytes or 8 KWords, two Parameter Blocks of 8 KBytes or 4 KWords, one Main Block of 32 KBytes or 16 KWords and one Main Blocks of 64 KBytes or 32 KWords. The M29F100T has the Boot Block at the top of the memory address space and the M29F100B locates the Boot Block starting at the bottom. The memory maps are showed in Figure 3. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any block not being ersased, and then resumed. Block protection provides additional data security. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application. Bus Operations The following operations can be performed using the appropriatebus cycles: Read (Array, Electronic Signature, Block Protection Status), Write command, Output Disable, Standby, Reset, Block Prot n , Unp t e cti on Verif y, Unprotection Verify and Block Temporary Unprotection. See Tables 4 and 5.


 

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