Details, datasheet, quote on part number: M295V102BB45K1T
PartM295V102BB45K1T
CategoryMemory => Flash
Description1 Mbit 64kb X16, Boot Block Single Supply Flash Memory
CompanyST Microelectronics, Inc.
DatasheetDownload M295V102BB45K1T datasheet
  

 

Features, Applications
1 Mbit (64Kb x16, Boot Block) Single Supply Flash Memory

SINGLE 5V10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 35ns PROGRAMMING TIME 8s per Word typical 5 MEMORY BLOCKS 1 Boot Block (Bottom Location) 2 Parameter and 2 Main Blocks

PROGRAM/ERASE CONTROLLER Embedded Word Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits

ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend

UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming TEMPORARY BLOCK UNPROTECTION MODE LOW POWER CONSUMPTION Standby and Automatic Standby

100,000 PROGRAM/ERASE CYCLES per BLOCK M28F102 COMPATIBLE Pin-out and Read Mode

20 YEARS DATA RETENTION Defectivity below 1 ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code: 0097h

Figure 2A. PLCC Connections Figure 2B. TSOP Connections

W RP VCC VSS NC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Supply Voltage Ground Not Connected Internally

SUMMARY DESCRIPTION The a 1 Mbit (64Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the

Symbol TA TBIAS TSTG VIO (2) VCC V ID Parameter Ambient Operating Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Identification Voltage Value to 13.5 Unit C V

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions.

process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, see Table 3, Block Addresses. The first 32 Kwords have been divided into four additional blocks. The 8 Kword Boot Block can be used for small initialization code to start the microprocessor, the two 4 Kword Parameter Blocks can be used for parameter storage and the remaining 16 Kwords are a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in PLCC44 and x 14mm) packages. Access times 50ns, 55ns and 70ns are available. The memory is supplied with all the bits erased (set to '1').

SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A15). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ15). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations DQ0-DQ7 represent the commands sent to the Command Interface of the internal state machine; the Command Interface does not use DQ8-DQ15 to decode the commands. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface.


 

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