|Category||Memory => Flash|
|Description||2 Mbit 256kb x8 or 128kb X16, Boot Block Single Supply Flash Memory|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download M295V200BB90N6T datasheet
|2 Mbit 128Kb x16, Boot Block) Single Supply Flash Memory
SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 45ns PROGRAMMING TIME 8µs per Byte/Word typical 7 MEMORY BLOCKS 1 Boot Block (Top or Bottom Location) 2 Parameter and 4 Main Blocks
PROGRAM/ERASE CONTROLLER Embedded Byte/Word Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy Output PinERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend
UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming TEMPORARY BLOCK UNPROTECTION MODE LOW POWER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1 ppm/year ELECTRONIC SIGNATURE Manufacturer Code: M29F200BT Device Code: M29F200BB Device Code: 00D4h
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
RP RB BYTE VCC VSS NC 2/22 Address Inputs Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select Supply Voltage Ground Not Connected Internally
SUMMARY DESCRIPTION The a 2 Mbit 128Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29F200B is fully backward compatible with the M29F200. The memory is divided into blocks that can be erased independently it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
Symbol Parameter Ambient Operating Temperature (Temperature Range Option 1) TA Ambient Operating Temperature (Temperature Range Option 6) Ambient Operating Temperature (Temperature Range Option 3) TBIAS TSTG VIO (2) VCC VID Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Identification Voltage Value to 13.5 Unit °C V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions.
The blocks in the memory are asymmetrically arranged, see Tables 3A and 3B, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered x 20mm) and SO44 packages. Access times 55ns, 70ns and 90ns are available. The memory is supplied with all the bits erased (set to '1'). SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A16). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands
sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). When BYTE is High, V IH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A1 Low will select the LSB of the Word on the other addresses, DQ15A1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface.
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