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Part: M29F080A-70N6T
Category:
Memory
-> Flash
Description: 8 Mbit 1mb X8, Uniform Block Single Supply Flash Memory
Company: ST Microelectronics, Inc.
Datasheet: Download M29F080A-70N6T datasheet File size : 1053 kB
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Datasheet text preview:
M29F080A
8 Mbit (1Mb x8, Uniform Block) Sing le Supply Flash Memory
s
SING LE 5V±10% SUPPLY VOLTAGE for PROG RAM, ERASE and READ OPERATIONS ACCESS TIME: 70ns PROG RAMMING TIME 8µs by Byt e typical
44
s s
s s
16 UNI FORM 64 Kbyte MEMORY BLOCKS PROG RAM/ERASE CONTROLLER Embedded Byte Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy Output Pin
TSOP 40 (N) 10 x 20mm SO 44 (M)
1
s
ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend Figure 1. Logic Diagram
s
TEMPORARY BLOCK UNPROTECTION MODE LOW PO WER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1 ppm/year ELECTRONIC SIGNATURE M anufacturer Code: 20h Device Code: F1h
A0-A19 W E G RP M29F080A RB VCC
s
s
20
8 DQ0-DQ7
s
s
VSS
AI00501C
April 2000
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M29F080A
Figure 2. TSOP Connections Figure 3. SO Connections
NC RP A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS VSS 1 2 3 4 5 6 7 8 9 10 11 M29F080A 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC E A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC W G RB DQ7 DQ6 DQ5 DQ4 VCC
A19 A18 A17 A16 A15 A14 A13 A12 E VCC NC RP A11 A10 A9 A8 A7 A6 A5 A4
1
40
10 11
M29F080A
31 30
20
21
AI00520B
NC NC W G RB DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
AI00521B
Table 1. Signal Names
A0-A19 DQ0-DQ7 E G W RP RB VCC VSS NC Address Inputs Dat a Inputs/Outputs Chip Enable Out put E nable Wr ite E nable Reset/Block Temporary Unprotec t Ready/Busy O utput Supply Voltage Gro und Not Connected Inte rnally
SUMMARY DESCRIPTION The M29F080A is an 8 Mbit (1Mb x8) non-volatile memory that c an be read, erased and reprogrammed. These operations can be performed us-
ing a single 5V supply. O n power-up t he memory defaults to i ts Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided i nto blocks that can be erased independently s o i t i s possible to preserve valid data while old data is erased. Blocks can be protected in groups to prevent accidental Program or Erase commands f rom modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions i dentified. The command set required t o control the memory is consistent wit h JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple c onnection to most microprocessors, often without additional logic. The m emory is offered in a TSOP40 (10 x 20mm) and SO44 packages and it is supplied with all the bits erased (set to '1').
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M29 F080 A
Table 2. Absolute Maximum Ratings (1)
Symb ol Parameter Ambient Operating Temperature (Temperature Range Option 1) TA Ambient Operating Temperature (Temperature Range Option 6) Ambient Operating Temperature (Temperature Range Opti on 3) TB IAS TS TG VIO (2) VCC V ID Temperature U nder Bias Storage Temperature Input or Output Voltage Supply Voltage Identification Voltage Value 0 to 70 40 t o 85 40 to 125 50 to 125 65 to 150 0.6 to 6 0.6 to 6 0.6 to 13.5 Unit °C °C °C °C °C V V V
Note: 1. Except for the rating " Operating T emperature R ange", stresses above those liste d in the Table "A bsolute Maximum R atings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above t hose indicated in t he Operating sections of t his s pecification is not impl ied. Exposure t o A bsolute M aximum R ating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot t o 2V during tr ansition and for les s t han 20ns during tr ansitions.
Table 3. Uniform Block A ddresses, M29F080A
# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Ran ge F0000h-FFFFFh 7 E 0000h-EFFFFh D 0000h-DFFFFh 6 C 0000h-CFFFFh B 0000h-BFFFFh 5 A 0000h-AFFFFh 9 0000h-9FFFFh 4 8 0000h-8FFFFh 7 0000h-7FFFFh 3 6 0000h-6FFFFh 5 0000h-5FFFFh 2 4 0000h-4FFFFh 3 0000h-3FFFFh 1 2 0000h-2FFFFh 1 0000h-1FFFFh 0 0 0000h-0FFFFh P rotection Group
SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent t o the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). T he Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations t hey represent the commands sent to the Command Interface of the internal state machine. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations t o be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, c ontrols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of th e memory's Command Interface. Reset/Block Temporary Unprotect (RP). T he Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to th e memory or to temporarily unprotect all blocks that have been protected.
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