|
|
Part: M29W400BT120N6
Category:
Description: 4 Mbit (512KB X8 or 256KB X16, Boot BLOCK) Low Voltage Single Supply Flash Memory
Company: ST Microelectronics, Inc.
Datasheet: Download M29W400BT120N6 datasheet File size : 840 kB
Request For quote: Find where to buy M29W400BT120N6
Datasheet text preview:
M29W400BT M29W400BB
4 Mbit (512Kb x8 or 256Kb x16, Boot Block) Low Voltage Single Supply Flash Memory
s
SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 55ns PROGRAMMING TIME 10µs per Byte/Word typical 11 MEMORY BLOCKS 1 Boot Block (Top or Bottom Location) 2 Parameter and 8 Main Blocks
FBGA
s s
s
TSOP48 (N) 12 x 20mm
TFBGA48 (ZA) 6 x 8 ball array
s
PROGRAM/ER ASE C ONTR OLLER Embedded Byte/Word Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy Output Pin
1 44
s
ERASE SU SPEND and RESUME MOD ES Read and Program another Block during Erase Suspend
SO44 (M)
s
UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming Figure 1. Logic D iagram TEMPORARY BLOCK UNPROTECTION M OD E LOW POWER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per B L OC K 20 YEARS DATA RETENTION Defectivity below 1 ppm/year
W E G RP M29W400BT M29W400BB DQ15A1 BYTE RB 18 A0-A17 VCC
s
s
s
15 DQ0-DQ14
s
s
ELECTRONIC SIGNATURE M anuf ac t urer C od e: 0020h Top Device Code M29W400BT: 00EEh Bottom Device Code M29W400BB: 00EFh
VSS
AI02934
June 2001
1/25
M29W400BT, M29W 400BB
Figure 2. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB NC A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Figure 3. SO Connections
12 M29W400BT 37 13 M29W400BB 36
NC RB A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 M29W400BT 12 M29W400BB 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
24
25
AI02935
AI02936
Table 1. Signal Names
A0-A17 DQ0-DQ7 DQ8-DQ14 DQ15A1 E G W RP RB BYTE VCC VSS NC Address Inputs Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select Supply Voltage Ground Not Connected Internally
SUMMARY DESCRIPTION The M29W 400B is a 4 Mbit (512Kb x8 or 256Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29W 400B is fully backward compatible with the M29W 400. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
2/25
M29W 400BT, M29W400BB
Figure 4. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A13
B
A4
A17
NC
RP
A8
A12
C
A2
A6
NC
NC
A10
A14
D
A1
A5
NC
NC
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15 A1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI03988
The blocks in the memory are asymmetrically arranged, see Tables 3 and 4, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often w ithout additional logic. The memory is offered in TSOP48 (12 x 20mm), TFBGA48 (0.8mm pitch) and SO44 packages and it is supplied with all the bits erased (set to '1').
3/25
Others parts begin by m2
|
|
|
