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Part: M29W800AT
Category:
Memory
-> Flash
-> NOR Flash
-> Industry Standard Single Supply 3V
Description: 8 Mbit (1MB X8 or 512KB X16, Boot BLOCK) Low Voltage Single Supply Flash Memory
Company: ST Microelectronics, Inc.
Datasheet: Download M29W800AT datasheet File size : 840 kB
Request For quote: Find where to buy M29W800AT
Datasheet text preview:
M29W800AT M29W800AB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Single Supply Flash Memory
s
2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 80ns PROGRAMMING TIME: 10µs typical PROGRAM/ER ASE CONTROLLER (P/E.C.) Program Byte-by-Byte or Word-by-Word Status Register bits and Ready/Busy Output
TSOP48 (N) 12 x 20mm TFBGA48 (ZA) 8 x 6 solder balls
FBGA
s s s
s s s
SEC URITY PROTECTION MEMORY AREA INSTRUCTION ADDRESS CODING: 3 digits MEMOR Y BLOCKS Boot Block (Top or Bottom location) Parameter and Main blocks
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BLOCK, MULTI-BLOCK and CHIP ERASE MULTI BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend Figure 1. Logic Diagram
SO44 (M)
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LOW POWER CONSUMPTION Stand-by and Automatic Stand-by
VCC
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100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year
A0-A18 W E G RP M29W800AT M29W800AB 19 15 DQ0-DQ14 DQ15A1 BYTE RB
s
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ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M29W800AT: D7h Bottom Device Code, M29W800AB: 5Bh
VSS
AI02599
June 2001
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M29W800AT, M29W800AB
Figure 2. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Figure 3. SO Connections
12 13
M29W800T M29W800B
37 36
RB A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
44 1 43 2 3 42 4 41 40 5 39 6 38 7 37 8 36 9 35 10 11 M29W800T 34 12 M29W800B 33 32 13 31 14 30 15 29 16 17 28 18 27 19 26 20 25 21 24 22 23
AI02181
RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
24
25
AI02179
Table 1. Signal Names
A0-A18 DQ0-DQ7 DQ8-DQ14 DQ15A1 E G W RP RB BYTE VCC VSS NC DU 2/34 Address Inputs Data Input/Outputs, Command Inputs Data Input/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Supply Voltage Ground Not Connected Internally Don't Use as Internally Connected
DESCRIPTION The M29W800A is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte or Word-by-Word basis using only a single 2.7V to 3.6V VCC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles. Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings. The device is offered in TSOP48 (12 x 20mm), SO44 and TFBGA48 0.8 mm ball pitch packages.
M29W 800AT, M29W800AB
Figure 4. TFBGA Connections (Top view through package)
1 2 3 4 5 6
A
A3
A7
RB
W
A9
A13
B
A4
A17
NC
RP
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
NC
NC
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15 A1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI00656
Organisation The M29W800A is organised as 1M x8 or 512K x16 bits selectable by the BYTE signal. When BYTE is Low the Byte-wide x8 organisation is selected and the address lines are DQ15A1 and A0-A18. The Data Input/Output signal DQ15A1 acts as address line A1 which selects the lower or upper Byte of the memory word for output on DQ0-DQ7, DQ8-DQ14 remain at High impedance. When BYTE is High the memory uses the address inputs A0-A18 and the Data Input/Outputs DQ0DQ15. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-level input provides a hardware reset when pulled Low, and when held High (at VID) temporarily unprotects blocks previously protected allowing them to be programed and erased. Erase and Program operations are controlled by an internal Program/ Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms.
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