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Part: M29W800AT120N6T
Category:
Memory
-> Flash
Description: 8 Mbit 1mb x8 or 512kb X16, Boot Block Low Voltage Single Supply Flash Memory
Company: ST Microelectronics, Inc.
Datasheet: Download M29W800AT120N6T datasheet File size : 840 kB
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Datasheet text preview:
M29W800AT M29W800AB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Sin gle Supply Flash Memory
s
2.7V to 3.6V SUPPLY VOLTAGE for PROG RAM, ERASE and READ OPERATIONS ACCESS TIME: 80ns PROG RAMMING TIME: 10µs typical PROG RAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte or Word-by-Word Status Register bits and Ready/Busy Output
1 44
s s s
s s s
SECURITY PROTECTION MEMORY AREA I NSTRUCTION ADDRESS COD ING: 3 digits MEMORY BLOCKS Boot Block (Top or Bottom location) Parameter and Main blocks
TSOP 48 (N) 12 x 20mm
SO44 (M )
FBGA
s s
BLOCK, MULTI-BLOCK and CHIP ERASE MULTI BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend
LFBG A48 ( ZA) 8 x 6 s older balls
s
Figure 1. Logic Diagram
s
LOW PO WER CONSUMPTION Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1ppm/year ELECTRONIC SIGNATURE M anufacturer Code: 20h T op Device Code, M29W800AT: D7h Bottom Device Code, M29W800AB: 5Bh
A0-A18 W E G RP
VCC
s
19
15 DQ0-DQ14 DQ15A1 M29W800AT M29W800AB BYTE RB
s
s
VSS
AI02599
Marc h 2000
1/33
M29W800AT, M2 9W 8 00A B
Figure 2. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
Figure 3. SO Connections
12 13
M29W800T M29W800B
37 36
RB A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M29W800T 34 12 M29W800B 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 24 21 22 23
AI02181
RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
24
25
AI02179
Table 1. Signal Names
A0-A18 DQ0-DQ7 DQ8-DQ1 4 DQ15A1 E G W RP RB BYTE VCC VSS NC DU 2/33 Address Inputs Dat a Input/Outputs, C ommand Input s Dat a Input/Outputs Dat a Input/Output or Address I nput Chip Enable Out put E nable Wr ite E nable Reset/Block Temporary Unprotec t Ready/Busy O utput Byte /Word Organization Supply Voltage Gro und Not Connected Inte rnally Don't Use as In ter nally Connected
DESCRIPTION The M29W800A is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte or Word-by-Word basis using only a single 2.7V to 3.6V VCC supply. For Program and Erase operations the necessary high voltages are generated internally. T he device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles. Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings. The device is offered in TSOP48 (12 x 20mm), SO44 and LFBGA48 0.8 mm ball pitch packages.
M29 W 80 0AT, M2 9W 800 AB
Figure 4. LFBGA Connections (Top view through package)
1 2 3 4 5 6 7 8
F
A13
A12
A14
A15
A16
BYTE
DQ15 A1
VSS
E
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
D
W
RP
DU
DU
DQ5
DQ12
VCC
DQ4
C
RB
DU
A18
DU
DQ2
DQ10
DQ11
DQ3
B
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A
A3
A4
A2
A1
A0
E
G
VSS
AI00656
Organisation The M29W800A is organised as 1M x8 or 512K x16 bits selectable by the BYTE signal. When BYTE is Low the Byte-wide x8 organisation is selected and the address lines are DQ15A1 and A0-A18. The Data Input/Output signal DQ15A1 acts as address line A1 which selects t he lower or upper Byte of the memory word for output on DQ0-DQ7, DQ8-DQ14 remain at High impedance. When BYTE is High the memory uses the address inputs A0-A18 and t he Data Input/Outputs DQ0DQ15. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. A Reset/Block Temporary Unprotection RP tri-level input provides a hardware reset when pulled Low, and when held High (at VID) te mporarily unprotects blocks previously protected allowing them to be programed and erased. Erase and Program operations are controlled by an internal Program/ Erase Controller (P/E.C.). Status R egister data output on DQ7 provides a Data Polling signal, and DQ6 and DQ 2 provide Toggle s ignals t o indicate the state of the P/E.C operations. A Ready/Busy RB output indicates the completion of the i nternal algorithms.
Memory Bl ocks The devices feature asymmetrically blocked architecture providing system memory integration. Both M29W800AT and M29W800AB devices have an array of 19 blocks, one Boot Block of 16 KBytes or 8 KWords, two Parameter Blocks of 8 KBytes or 4 KWords, one Main Block of 32 KBytes or 16 KWords and fifteen Main Blocks of 64 KBytes or 32 KWords. The M29W800AT has t he Boot Block at the t op of the memory address space and the M29W800AB locates the Boot Block starting at the bottom. The memory maps are showed in Figure 5. Each block can be erased separately, any combination of blocks can be specified fo r m ulti-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/ E.C. The block erase operation can be suspended in order to read f rom or program to any block not being erased, and then resumed. Block protection provides additional data s ecurity. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application.
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