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Part: M45PE80-V
Category:
Memory
-> Flash
-> Serial Flash
-> Serial Flash for Data Storage
Description: 8 Mbit, Low Voltage, Page-erasable Serial Flash Memory With Byte-alterability And a 25 MHZ Spi Bus Interface
Company: ST Microelectronics, Inc.
Datasheet: Download M45PE80-V datasheet File size : 1417 kB
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Datasheet text preview:
M45PE80
8 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus Interface
PRELIMINARY DATA
FEATUR ES SUMMARY s 8Mbit of Page-Erasable Flash Memory
s s
Figure 1. Packages
Page Write (up to 256 Bytes) in 12 ms (typical) Page Program (up to 256 Bytes) in 2 m s (typical) Page Erase (256 Bytes) in 10 ms (typical) Sector Erase (512 Kbit) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Interface 25 MHz Clock Rate (maximum) Deep Power-down Mode 1 ľA (typical) More than 100,000 Write Cycles More than 20 Year Data Retention
VFQFPN8 (MP) (MLP8)
s s s s s s s s
June 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M45PE80
SUMMARY DESCRIPTION The M45PE80 is a 8Mbit (1M x 8 bit) Serial Paged Flash Memory accessed by a high speed SPIcompatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle. The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1,048,576 bytes. The memory can be erased a page at a time, using the Page Erase instruction, or a sector at a time, using the Sector Erase instruction. Figure 2. Logic Diagram
VCC
Note: 1. See page 28 (onwards) for package dimensions, and how to identify pin-1.
Figure 3. QFP Connections
M45PE80 D C Reset S 1 2 3 4 8 7 6 5
AI06811B
Q VSS VCC W
D C S W Reset M45PE80
Q
VSS
AI06810B
Table 1. Signal Names
C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Reset Supply Voltage Ground
S
W Reset VCC VSS
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M 45PE80
SIGNA L DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Reset (Reset). The Reset (Reset) input provides a hardware reset for the memory. In this mode, the outputs are high impedance. When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode, provided that no internal operation is currently in progress. Driving Reset (Reset) Low while an internal operation is in progress has no effect on that internal operation (a write cycle, program cycle, or erase cycle). Write Protect (W). This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is connected to VSS, causing the first 256 pages of memory to become read-only by protecting them from write, program and erase operations. When Write Protect (W) is connected to VCC, the first 256 pages of memory behave like the other pages of memory.
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