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Part: M54HC4020F1R
Category:
Logic
-> Counters
-> Binary Counters
Description: Hc4020 14 Stage Binary Counter Hc4040 12 Stage Binary Counter
Company: ST Microelectronics, Inc.
Datasheet: Download M54HC4020F1R datasheet File size : 254 kB
Request For quote: Find where to buy M54HC4020F1R
Datasheet text preview:
M54/74HC4020 M5 4 /74 H C 40 40
HC4020 14 STAGE BINARY COUNTER HC4040 12 STAGE BINARY COUNTER
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HIGH SPEED fMAX = 73 MHz (TYP.) at VCC = 5 V LOW POWER DISSIPATION o ICC = 4 ľA (MAX.) at TA = 25 C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 4020B/4040B
B1 R (Plastic Package)
F 1R (Ceramic Package)
M 1R (Micro Package)
C1R (Chip Carrier)
O RD E R CO D E S : M 54HC X X X F 1 R M 74 HC X X X M 1R M 74HC X X X B 1R M 74H CX X X C1 R
D ESCRI PTI ON The M54/74HC4020/HC4040 are high speed CMOS 14/12-STAGE BINARY COUNTER fabricated in silicon gate C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low consumption. A clear input is used to reset the counter to the all low level state. A high level on CLEAR accomplishes the reset function. A negative transition on the CLOCK input increments the counter by one. For HC4020 twelve kind od divided output are provided; 1st and 4th s tage to 14th stage. PIN CO N NEC TI ON (t op v i ew)
H C4 02 0 H C4 04 0 HC 4020 HC 4040
The maximum division available at last s tage is 1/16384 x fIN at clock. For HC4040 each division stage has an output; the final frequency is 1/4096 x fIN. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
March 1993
1/13
M 54 / M 7 4H C 4 0 2 0/ 40 4 0
INPUT A N D OU T PUT EQ UI VAL ENT C I RC UI T
P I N D E SC R I P T I O N ( H C 40 20 )
PIN No 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 10 11 8 16 SYMBOL Q1, Q4 to Q14 NAME AND FUNCTION Parallel Outputs
P I N D ES C R I PT I O N ( H C 4 04 0)
PIN No 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 10 11 8 16 SYMBOL Q1 to Q12 NAME AND FUNCTION Parallel Outputs
CLOCK CLEAR GND V CC
Clock Input (LOW to HIGH, edge triggered) Reset Inputs Ground (0V) Positive Supply Voltage
CLOCK CLEAR GND VCC
Clock Input (LOW to HIGH, edge triggered) Reset Inputs Ground (0V) Positive Supply Voltage
I EC L OG IC SYMBO L S
HC 40 20 H C404 0
TR U TH T AB LE
CLOCK X CLEAR H L L OUTPUT STATE ALL OUTPUTS = "L" NO CHANGE ADVANCE TO NEXT STATE
2/13
M 54 / M 7 4 H C 4 02 0 / 4 0 40
LOGIC DIA G RA M (HC 4020)
3/13
Others parts begin by m5
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