35 V OPERATION 5.1 V REFERENCE TRIMMED TO 500 KHz OSCILLATOR RANGE SEPARATE OSCILLATOR SYNC TERMINAL ADJUSTABLE DEADTIME CONTROL INTERNAL SOFT-START PULSE-BY-PULSE SHUTDOWN INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LATCHING PWM TO PREVENT MULTIPLE PULSES DUAL SOURCE/SINK OUTPUT DRIVERS
DESCRIPTION The SG3525A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip 5.1 V reference is trimmed 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time ad- justment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately mV of hysteresis for jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525A output stage features NOR logic, giving a LOW output for an OFF state.
Symbol Vi VC IOSC IR IT Supply Voltage Collector Supply Voltage Oscillator Charging Current Output Current, Source or Sink Reference Output Current through CT Terminal Logic Inputs Analog Inputs Total Power Dissipation at Tamb 70 °C Junction Temperature Range Storage Temperature Range Operating Ambient Temperature SG2525A SG3525A Parameter Value to 70 Unit mW °C
Symbol Rth j-pins Rth j-amb Rth j-alumina Parameter Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Thermal Resistance Junction-alumina Max 80 50 Unit °C/W
* Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 0.65 mm thickness with infinite heatsink.
ELECTRICAL CHARACTERISTICS (V# 20 V, and over operating temperature, unless otherwise specified)
VREF/T* Temp. Stability * Total Output Variation Short Circuit Current * VREF* f/T* fMIN fMAX Output Noise Voltage Long Term Stability Initial Accuracy Voltage Stability Temperature Stability Minimum Frequency Maximum Frequency Current Mirror Clock Amplitude Clock Width Sync Threshold Sync Input Current VOS Ib Ios * Input Offset Voltage Input Bias Current Input Offset Current DC Open Loop Gain Bandwidth Product DC Transconduct. Output Low Level Output High Level CMR PSR Comm. Mode Reject. Supply Voltage Rejection