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Part: SG3525A
Category:
Power Management
-> PWM Power Supply
Description: Regulating Pulse Width Modulators
Company: ST Microelectronics, Inc.
Datasheet: Download SG3525A datasheet File size : 611 kB
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Datasheet text preview:
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SG2525A S G3 525 A
REGULATING PULSE WIDTH MODULATORS
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8 TO 35 V OPERATION 5.1 V REFERENCE TRIMMED TO ± 1 % 100 Hz TO 500 KHz OSCILLATOR RANGE SEPARATE OSCILLATOR SYNC TERMINAL ADJUSTABLE DEADTIME CONTROL INTERNAL SOFT-START PULSE-BY-PULSE SHUTDOWN INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LATCHING PWM TO PREVENT MULTIPLE PULSES DUAL SOURCE/SINK OUTPUT DRIVERS
DIP16
16(Narrow)
D E SC R I P T I O N The SG3525A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to ± 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time ad- justment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525A output stage features NOR logic, giving a LOW output for an OFF state.
P I N CONNECTIONS AND ORDERING NUMBERS (top view)
Type SG2525A SG3525A
Plastic DIP SG2525AN SG3525AN
SO16 SG2525AP SG3525AP
June 2000
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SG2525A-SG3525A
ABSOLUTE MAXIMUM RATINGS
Symbol Vi VC IOSC Io IR IT Supply Voltage Collector Supply Voltage Oscillator Charging Current Output Current, Source or Sink Reference Output Current Current through CT Terminal Logic Inputs Analog Inputs Total Power Dissipation at Tamb = 70 °C Junction Temperature Range Storage Temperature Range Operating Ambient Temperature : SG2525A SG3525A Parameter Value 40 40 5 500 50 5 0.3 to + 5.5 0.3 to Vi 1000 55 to 150 65 to 150 25 to 85 0 to 70 Unit V V mA mA mA mA V V mW °C °C °C °C
Ptot Tj Tstg Top
THERMAL DATA
Symbol Rth j-pins Rth j-amb Rth j-alumina Parameter Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Thermal Resistance Junction-alumina (*) Max Max Max SO16 DIP16 50 80 50 Unit °C/W °C/W °C/W
* Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 × 20 mm ; 0.65 mm thickness with infinite heatsink.
B L O C K DIAGRAM
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SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS (V# i = 20 V, and over operating temperature, unless otherwise specified)
Symbol Parameter Test Conditions Min. REFERENCE SECTION VREF VREF VREF Output Voltage Line Regulation Load Regulation Tj = 25 °C Vi = 8 to 35 V IL = 0 to 20 mA Over Operating Range Line, Load and Temperature VREF = 0 Tj = 25 °C 10 Hz f 10 kHz, Tj = 25 °C Tj = 125 °C, 1000 hrs Tj = 25 °C Vi = 8 to 35 V Over Operating Range RT = 200 K CT = 0.1 µF RT = 2 K CT = 470 pF IRT = 2 mA Tj = 25 °C Sync Voltage = 3.5 V 400 1.7 3 0.3 1.2 2 3.5 0.5 2 1 0.5 1 RL 10 M Gv = 0 dB T j = 25 °C 60 1 1.1 75 2 1.5 0.2 3.8 VCM = 1.5 to 5.2 V Vi = 8 to 35 V 60 50 5.6 75 60 0.5 3.8 60 50 1 2.8 2.5 5 10 1 60 1 1.1 75 2 1.5 0.2 5.6 75 60 0.5 2.2 5 80 40 20 ±2 ± 0.3 ±3 5.05 5.1 10 20 20 5.15 20 50 50 5.2 100 200 50 ±6 ±1 ±6 120 400 1.7 3 0.3 1.2 2 3.5 0.5 2 1 2 1 1 2.8 2.5 10 10 1 2.2 4.95 80 40 20 ±2 ±1 ±3 5 5.1 10 20 20 5.2 20 50 50 5.25 100 200 50 ±6 ±2 ±6 120 V mV mV mV V mA µVrms mV % % % Hz KHz mA V µs V mA mV µA µA dB MHz ms V V dB dB SG2525A Typ. Max. Min. SG3525A Typ. Max. Unit
VREF/T* Temp. Stability * Total Output Variation Short Circuit Current * VREF* *, · *, · f/T* fMIN fMAX *, · *, · Output Noise Voltage Long Term Stability Initial Accuracy Voltage Stability Temperature Stability Minimum Frequency Maximum Frequency Current Mirror Clock Amplitude Clock Width Sync Threshold Sync Input Current VOS Ib Ios * *, Input Offset Voltage Input Bias Current Input Offset Current DC Open Loop Gain Gain Bandwidth Product DC Transconduct. Output Low Level Output High Level CMR PSR Comm. Mode Reject. Supply Voltage Rejection
OSCILLATOR SECTION * *
ERROR AMPLIFIER SECTION (VCM = 5.1 V)
30 K RL 1 M Tj = 25 °C
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