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Part: ST20GP1X33S
Category:
Communication
-> Wireless
-> GPS (Global Positioning Systems)
Description: GPS Processor
Company: ST Microelectronics, Inc.
Datasheet: Download ST20GP1X33S datasheet File size : 99 kB
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Datasheet text preview:
®
ST20-GP1
GPS PROCESSOR
FEATURES s Applicat ion specific features · 12 channel GPS correlation DSP hardware and ST20 CPU (for control and position caluculations) on one chip · no TCXO required · RTCA-SC159 / WAAS / EGNOS supported s GPS performance · accuracy - stand alone with SA on <100m, SA off <30m - differential <1m - surveying <1cm · time to first fix - autonomous start 90s - cold start 45s - warm start 7s - obscuration 1s s 32-bit ST20 CPU · 16/33 MHz processor clock · 25 MIPS at 33 MHz · fast integer/bit operations s 4 Kbytes on-chip SRAM · 130 Mbytes/s maximum bandwidth s Programmable memory interface · 4 separately configurable regions · 8/16-bits wide · support for mixed memory · 2 cycle external access s Serial communications · Programmable UART (ASC) · OS-Link s Vectored interrupt subsystem · 2 dedicated interrupt pins · 5 levels of interrupt s Power management · low power operation · power down modes s Professional toolset support · ANSI C compiler and libraries · INQUEST advanced debugging tools s Technology · Static clocked 50 MHz design · 3.3 V, sub micron technology s 100 pin PQFP package
September 2003
GPS radio ST20-GP1
12 channel GPS hardware DSP
ST20 CP U
Low power controller Real time clock/calendar
Interrupt controller
Serial com munications 2 UART (ASC) 1 OS-Link Parallel input/output
4K SRAM
. . . . . .
6
Programmable mem ory interface
Byte-wide parallel port
8
RA M
RO M/ FLASH
APPLICATIONS s Global Positioning System (GPS) receivers s Car navigation systems s Fleet management systems s Time reference for telecom systems
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Contents
1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ST20-GP1 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. 1 DSP module registers .........13
4
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. 1 4. 2 4. 3 4. 4 4. 5 4. 6 Registers .....18 Processes and concurrency ........19 Priority .........21 Process communications ....21 Timers .........22 Traps and exceptions .........23
5
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. 1 5. 2 5. 3 5. 4 5. 5 5. 6 Interrupt vector table ...........29 Interrupt handlers ..........29 Interrupt latency ...30 Pre-emption and interrupt priority .........30 Restrictions on interrupt handlers .........30 Interrupt configuration registers ...31
6
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6. 1 6. 2 6. 3 Instruction cycles ..........34 Instruction characteristics ............35 Instruction set tables ...........36
7
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7. 1 7. 2 7. 3 System memory use ...........45 Boot ROM ............46 Internal peripheral space ....46
8
Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8. 1 SR AM .........49
9
Programmable memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9. 1 9. 2 9. 3 EMI signal descriptions .......51 Strobe allocation ..52 External accesses ......52
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®
ST20-GP1
9. 4 9. 5 9. 6
MemW ait .....56 EMI configuration registers ..........58 Reset and bootstrap behavior ......59
10 Clocks and low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10. 1 10. 2 10. 3 10. 4 Clocks .........61 Low power control ......61 Low power configuration registers ........63 Clocking sources ..........65
11 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11. 1 11. 2 Reset, initialization and debug .....67 Bootstrap ....68
12 Serial link interface (OS-Link) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12. 1 12. 2 12. 3 OS-Link protocol ..70 OS-Link speed .....70 OS-Link connections ...........71
13 UART interface (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13. 1 13. 2 13. 3 13. 4 13. 5 Asynchronous serial controller operation ....73 Hardware error detection capabilities .........76 Baud rate generation ..........76 Interrupt control ....77 ASC configuration registers .........79
14 Parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14. 1 PIO Port ......85
15 Byte-wide parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
15. 1 15. 2 15. 3 15. 4 EMI mode operation ...........88 Parallel link (DMA) mode operation ............88 Configuration registers ........88 External data transfer protocols ...89
16 Configuration register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 17 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 18 GPS Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
18. 1 18. 2 Accuracy ............100 Time to first fix ...101
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