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Part: ST20GP6

Category:
 Communication
   -> Wireless
     -> GPS (Global Positioning Systems)

Description: GPS Processor

Company: ST Microelectronics, Inc.

Datasheet: Download ST20GP6 datasheet     File size : 99 kB

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Datasheet text preview:
®
ST20-GP6
GPS PROCESSOR
PRELIMINARY DATA
FEATURES s Application specific features · 12 channel GPS correlation DSP hardware, ST20 CPU (for control and position calculations) and memory on one chip · no TCXO required · RTCA-SC159 / WAAS / EGNOS supported s GPS performance · accuracy - stand alone with SA on <100m, SA off <30m - differential <1m - surveying <1cm · time to first fix - autonomous start 90s - cold start 45s - warm start 7s - obscuration 1s s Enhanced 32-bit VL-RISC CPU - C2 core · 16/33/50 MHz processor clock · 25 MIPS at 33 MHz · fast integer/bit operations s 64 Kbytes on-chip SRAM s 128 Kbytes on-chip ROM s Programmable memory interface · 4 separately configurable regions · 8/16-bits wide · support for mixed memory · 2 cycle external access s Programmable UART (ASC) s Parallel I/O s Vectored interrupt subsystem s Diagnostic control unit s Power management · low power operation · power down modes s Professional toolset support · ANSI C compiler/link driver and libraries · Debugging/profiling and simulation tools s Technology · Static clocked 50 MHz design · 3.3 V, sub micron technology s 100 pin PQFP package s JTAG Test Access Port
December 1998 The information in this datasheet is subject to change
GPS radio ST20-GP6
12 channel GPS hardware DSP
ST20 CPU
Low power controller Real time clock/calendar
Interrupt controller
Serial communications 2 UART (ASC)
Programmable memory interface
Parallel input/output
. 16 . .
64K SRAM
Diagnostic control unit
128K optional mask ROM
Test access port
APPLICATIONS s Global Positioning System (GPS) receivers s Car navigation systems s Fleet management systems s Time reference for telecom systems
42 1707 02 1/123
ST20-GP6
Contents
1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST20-GP6 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
5 7 11
DSP module registers ......... 13
4
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 4.2 4.3 4.4 4.5 4.6 Registers ..... Processes and concurrency ........ Priority ......... Process communications .... Timers ......... Traps and exceptions .........
19
19 20 22 23 23 24
5
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 5.2 5.3 5.4 5.5 5.6 Interrupt vector table ........... Interrupt handlers .......... Interrupt latency ... Preemption and interrupt priority .......... Restrictions on interrupt handlers ......... Interrupt configuration registers ...
30
31 31 32 32 33 33
6
Interrupt level controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 6.2
37
Interrupt assignments ......... 37 Interrupt level controller registers ......... 37
7
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 7.2 7.3
40
Instruction cycles .......... 40 Instruction characteristics ............ 41 Instruction set tables ........... 42
8
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 8.2 8.3
51
System memory use ........... 51 Boot ROM ............ 52 Internal peripheral space .... 52
9
Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 9.2
55
SRAM ......... 55 ROM ........... 55
2/123
ST20-GP6 10 Programmable memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1 10.2 10.3 10.4 10.5 10.6 EMI signal descriptions ....... External accesses ...... MemWait ..... EMI configuration registers .......... Boot source .......... Default configuration ...........
56
58 59 60 62 65 65
11 Low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 11.2
66
Low power control ...... 66 Low power configuration registers ........ 67
12 Real time clock and watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 12.2 12.3 12.4 Power supplies .... Real time clock .... Watchdog timer .... RTC/WDT configuration registers .........
70
70 70 70 71
13 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1 13.2 13.3
73
Reset, initialization and debug ..... 73 Bootstrap .... 73 Clocks ......... 73
14 Diagnostic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.1 14.2 14.3 14.4 14.5 14.6 Diagnostic hardware ........... Access features ... Software debugging features ....... Controlling the diagnostic controller ............ Peeking and poking the host from the target ....... Abortable instructions .........
75
75 76 77 79 80 80
15 UART interface (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1 15.2 15.3 15.4 15.5 Functionality ......... Timeout mechanism ........... Baud rate generation .......... Interrupt control ... ASC configuration registers .........
82
82 85 85 86 88
16 Parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.1
94
PIO Ports0-1 ........ 94
17 Configuration register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
3/123


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