|Category||Communication => Telephony => Line Card|
|Description||Northenlite G.lite DMT Transceiver|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download STLC1510 datasheet
ATM transport Forward Error correction & interleaving Framing & de-framing DMT modulation and demodulation Start-up & showtime control processing
In addition, the STLC1510 provides the following features: s Serial and Parallel network interface at backend to CO equipment
Serial interface to the AFE chip STLC1511 Access to off chip memory Power-up boot program stored in ROM 132 balls 12x12x1.7 mm LBGA package Power Consumption: 0.75 Watt Power Supp.: 2.5 V (core) and 3.3 V (I/O ring)
1.0 GENERAL DESCRIPTION The is a high-speed modem chip that provides the digital portion a G.992.2 DSL access at a Central Office (CO) site. It provides downstream and upstream data transport between an ATM byte stream and an analog front-end chip using Discrete Multi-Tone (DMT) Modulation. The STLC1510 is compliant with ITU-T G.992.2 (G.Lite), G.996.1 (G.Test), G.994.1 (G.Handshake), G.997.1 (G.Ploam).RxClk R xClav RxEnb RxSOC URxD ata[7:0] RxAddr[4:0] RxP arity
TxClk TxClav TxEnb TxSOC TxData[7:0] TxAddr[4:0] TxParity TxBP
This is preliminary information on a new product now in development. Details are subject to change without notice.
2.0 LIST OF MAIN BLOCKS The STLC1510 G.lite DMT Transceiver is formed by the following blocks (refer to Figure 1.): Embedded Processor Module (EPM) The EPM includes two embedded processor cores: the ARM7TDMI, a RISC microprocessor, and the a 16-bit DSP processor. The RISC microprocessor handles the chip control, G.Lite start-up and showtime control and DSP initialization. It also implements the Framing and Interleaving/Deinterleaving function required by G.992.2 standard. Block Processing Unit (BPU) Computationally intensive digital signal processing functions are performed in this engine. This engine utilizes customized DSP architecture that includes two multiplier/accumulator (MAC). Digital Front-End (DFE) This block provides the interface to an external analog front-end (AFE) device. This block provides decimation, interpolation for the signal sample for the ADC and DAC on the AFE and signal level monitoring for the analog AGC. Network Interface (NIF) The NIF is a selectable interface that carries the ATM signals to and from the STLC1510. This interface supports one parallel interface (Utopia Level or a serial data interface. The NIF includes a FIFO to buffer the data between the clock domains of the backend interface and the internal clock. Forward Error-Correction (FEC) The Forward Error Correction is done using ReedSolomon Coding. The R-S FEC encoding is performed byte-wise in the transceiver on the transmitted bytes. The two basic parameters that determine the performance of the code are the code word size, which consists of one or more DMT symbols (S), and the number of redundant check bytes R. Mapper/De-mapper Block (MAP) The Mapper/De-mapper Block (MAP) performs the bit packing and un-packing and constellation encoder/decoder for a G.992.2 DSL modem. This block also supports generation of Reverb and medley. Timing Generation Block (TGB) The timing generation block generates global clock and synchronization signals for the STLC1510. It uses the input clock signals to derive the main internal and output clock signals, as well as all synchronization pulses required to coordinate timing between the sub-blocks. Test Access Port (TAP) This block provides the test access to the STLC1510 using JTAG and BIST techniques. HPI Interface A host processor interface is provided to allow the to be optionally controlled by an external microcontroller. 3.0 TRANSIENT ENERGY CAPABILITIES 3.1 ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM). The pins of the device are to be able to withstand minimum 2000V for the HBM. 3.2 Latch-up The maximum sink or source current from any pin is limited 200mA to prevent latch-up. 4.0 ABSOLUTE MAXIMUM RATINGS The absolute maximum ratings, as specified below, are those ratings beyond which the device's lifetime may be impaired. The meeting of electrical specifications is not implied when the device is subjected to the absolute limits. The following table identifies the device's minimum and maximum ratings and along with the operatingconditions they define the limits for testing the deviceSYMBOL VDD3_3 VDD2_5 Tamb VIN, VOUT VIN5, VOUT5 IIN, IOUT PD Vesd I latchup
PARAMETER 3.3V Supply voltage w.r.t. VSS (0V) 2.5V Supply voltage w.r.t. VSS (0V) Ambient temperature Voltage at any 3.3V standard input or output Voltage at any 5V compatible input or output1 Current at any input or outputs Power dissipation Electrostatic Protection I/O Latch-up Current V > Vdd
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