|Description||Quad Feeder Power Supply|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download STLC5444B1 datasheet
SUPPLIES POWER FOR UP TO FOUR DIGITAL TELEPHONE LINES CONFORMS TO THE CCITT RECOMMENDATIONS FOR POWER FEED AT THE OR T REFERENCE POINTS SUPPORTS POINT-TO-POINT AND POINT TO MULTIPOINT CONFIGURATIONS EACH OF THE FOUR LINES IS INDIVIDUALLY CONTROLLED HIGH-VOLTAGE BCD TECHNOLOGY SUPPORTING TO -130V AUTOMATIC THERMAL SHUTDOWN STATUS CONDITION DETECTION (BY MICROPROCESSOR) FOR EACH LINE: Low output voltage Openloop Current overload Thermal overload Normal line condition PROGRAMMABLE CURRENT LIMITING OUTPUT CURRENT TO 120mA DESCRIPTION The ISDN Quad Feeder Power Supply (IQFPS) provides a power source for up to four line interfaces. The power source to the device is a local battery or a centralized regulated power supply. It can operate in point-to-point and point-to-multipoint configurations as far as S interface is concerned. By the device microprocessor interface, each powered line is individually controlled and monitored. Therefore, overloads and faults are easy to detect and localize even in a large system. The status conditions detected by the device on each line that may be read by the microprocessor are : low output voltage openloop current overload thermal overload normal line conditions A hardware current limiting programmable feature is available.STATUS DETECTOR S DRIVERS DISABLE LINE STATUS BUS S DRIVERS
ADDRESS BUS 0/2 O/3 INDIRECT ADDRESS REGISTER BIT 3 INT EN INPUT BUS D3/D0 LINE ENABLE REGISTER LER EN µP INTERFACE
Bit 0 of the tri state I/O data bus Active low interrupt output for the µP (open drain) Battery supply line (negative battery`s terminal)
Battery ground line +5V supply line Current limit programming Output of the power switch controller 0 Output of the power switch controller 1 Output of the power switch controller 2 Reserved pin: it must be left floating Output of the power switch controller 3 Active high reset input Active low read input Active low chip select input Active low write input Active high address latch enable Digital ground Address bit for R/W operations on the data bus Bit 3 of the I/O tri state data bus Bit 2 of the I/O tri state data bus
FUNCTIONAL DESCRIPTION ADDRESS LINE (Input) A0 selects source and destination locations for read and write operations on the data bus. A0 must be valid on the falling edge of ALE or during RD and WR if ALE is tied High. ALE - Address Latch Enable (Input; Active High) ALE is an input control pulse used to strobe the address on the A0 line into the address latch. This signal is active High to admit the input address. The address is latched on the High-Low transition of ALE. While ALE is High, the address latch is transparent. For an unmultiplexed microprocessor bus, ALE must be tied High.
BGND - Ground Battery CS - Chip Select (Input; Active Low) CS must be Low to enable the read or write operations of the device. Data transfer occurs over the D3-D0 lines. D3-D0 - DATA BUS (Input/Output; Three-State) The four bidirectional data bus lines are to exchange information with a microprocessor. D0 is the least significant bit and D3 is the most significant bit. A High on the data bus corresponds to a logical 1. These lines act as input when WR and CS are active and as output when RD and CS are active. When CS is inactive, the D3-D0 pins are placed in a high-impedance state.
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