Details, datasheet, quote on part number: STLC5466
PartSTLC5466
CategoryCommunication => ISDN
Description64 Channel-multi HDLC With N X 64KB/S Switching Matrix Associated
CompanyST Microelectronics, Inc.
DatasheetDownload STLC5466 datasheet
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Features, Applications
64 CHANNEL-MULTI HDLC WITH X 64KB/S SWITCHING MATRIX ASSOCIATED

64 TX HDLCs with broadcasting capability and/ or CSMA/CR function with automatic restart in case of Tx frame abort 64 RX HDLCs including Address Recognition 16 Command/Indicate Channels or 6-bit primitive) 16 Monitor Channels processed in accordance with GCI x 256 Switching Matrix without blocking and with Time Slot Sequence Integrity and loopback per bidirectional connection DMA Controller for 64 Tx Channels and 64 Rx Channels HDLCs AND DMA CONTROLLER ARE CAPABLE OF HANDLING A MIX OF LAPD,LAPB, SS7, CAS AND PROPRIETARY SIGNALLINGS External shared memory access between DMA Controller and Micro processor SINGLE MEMORY SHARED BETWEEN n x MULTI-HDLCs AND SINGLE MICRO PROCESSOR ALLOWS TO HANDLE x 64 CHANNELS Bus Arbitration Interface for various or 32 bit Microprocessors with fetch memory to accelerate the exchanges between Microprocessor and SHARED MEMORY SDRAM Controller allows to inter face to 16 Megabytes of Synchronous Dynamic RAM Interrupt Controller to store automatically events in shared memory Boundary scan for test facility TQFP176 package HCMOS6; 0.35 micron; 3.3volts +/-5% Operating temperature: to +85 °/C

DESCRIPTION The is a Subscriber line interface card controller for Central Office, Central Exchange, NT2 and PBX capable of handling:

16 U Interfaces or 2 Megabits line interface cards or 16 SLICs (Plain Old Telephone Service) or Mixed analogue and digital Interfaces (SLICs or U Interfaces) 16 S Interfaces Switching Network with centralized processing.

TQFP176 (Plastic Quad Flat Pack) ORDERING NUMBER: STLC5466

TABLE OF CONTENTS I.3.3 II III III.3.1 III.3.2 PIN INFORMATION................................................................................................................6 PIN CONNECTIONS..............................................................................................................6 PIN DESCRIPTION..............................................................................................................7 PIN DEFINITION.................................................................................................................12 Input Pin Definition................................................................................................................12 Output Pin Definition............................................................................................................12 Input/Output Pin Definition..................................................................................................12 BLOCK DIAGRAM...............................................................................................................13 FUNCTIONAL DESCRIPTION.............................................................................................13 THE SWITCHING MATRIX 64 KBITS/S........................................................................13 Function Description.............................................................................................................13 Architecture of the Matrix.....................................................................................................13 Connection Function............................................................................................................13 Loop Back Function.............................................................................................................15 Delay through the Matrix......................................................................................................15 Variable Delay Mode........................................................................................................15 Sequence Integrity Mode..................................................................................................15 Connection Memory.............................................................................................................15 Description.......................................................................................................................15 Access to Connection Memory.........................................................................................15 Access to Data Memory....................................................................................................15 Switching 32 Kbit/s...........................................................................................................15 Switching 16 Kbit/s...........................................................................................................16 HDLC CONTROLLER.........................................................................................................16 Function description.............................................................................................................16 Format of the HDLC Frame..............................................................................................16 Composition of an HDLC Frame.......................................................................................16 Description and Functions of the HDLC Bytes..................................................................16 CSMA/CR Capability............................................................................................................17 Time Slot Assigner Memory.................................................................................................17 Data Storage Reception..........................................................................................................................18 Transmission.....................................................................................................................18 Frame Relay.....................................................................................................................18 Transparent Modes..............................................................................................................18 Command of the HDLC Channels........................................................................................19 Reception Control.............................................................................................................19 Transmission Control........................................................................................................19 C/I AND MONITOR.............................................................................................................19 Function Description............................................................................................................19 GCI and V* Protocol.............................................................................................................19

VI.2 VI.3 Structure of the Treatment...................................................................................................20 CI and Monitor Channel Configuration..................................................................................20 CI and Monitor Transmission/Reception Command.............................................................20 SCRAMBLER AND DESCRAMBLER.................................................................................20 CONNECTION BETWEEN "ISDN CHANNELS" AND GCI CHANNELS..............................20 MICROPROCESSOR Description...........................................................................................................................21 Buffer...................................................................................................................................21 Write FIFO........................................................................................................................21 Read Fetch Memory.........................................................................................................23 Definition of the Interface for the different microprocessors..............................................23 MEMORY INTERFACE......................................................................................................23 Function Description............................................................................................................23 Choice of memory versus microprocessor and capacity required........................................23 Memory Cycle.......................................................................................................................23 Memories composed of different circuits..............................................................................23 Memory obtained with 1M x16 SDRAM circuit..................................................................23 Memory obtained with x 8 SDRAM circuit...................................................................23 Memory obtained with x 8 SDRAM circuit...................................................................23 Memory obtained with x 16 SDRAM circuit.................................................................24 BUS ARBITRATION...........................................................................................................24 CLOCKS.............................................................................................................................24 Clock Distribution Selection and Supervision.......................................................................24 VCXO Frequency Synchronization.......................................................................................24 INTERRUPT CONTROLLER..............................................................................................25 Description..........................................................................................................................25 Operating Interrupts (INT0 Pin)............................................................................................25 Time Base Interrupts (INT1 Pin)..........................................................................................25 Emergency Interrupts (WDO Pin)......................................................................................... 25 Interrupt WATCHDOG.......................................................................................................................25 RESET................................................................................................................................25 BOUNDARY DC SPECIFICATIONS..........................................................................................................27 LIST OF REGISTERS..........................................................................................................29 INTERNAL REGISTERS......................................................................................................31 IDENTIFICATION AND DYNAMIC COMMAND REGISTER... IDCR (00)H.........................31 GENERAL CONFIGURATION REGISTER GCR1 (02)H........................31 INPUT MULTIPLEX CONFIGURATION REGISTER IMCR0 (04)H.......................33


 

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